82845MP datasheet(63/157 Pages) INTEL

63 / 157 page

Intel

® 82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.19.

DERRSYN – DRAM Error Syndrome Register

Address Offset:

86h

Default Value:

00hb

Access:

Read Only

Size:

8 bits

This register is used to report the ECC syndromes for each quadword of a 32-Byte aligned data quantity

read from the DRAM array.

Bit

Description

7:0

DRAM ECC Syndrome (DECCSYN) (RO): After a DRAM ECC error, hardware loads this field with

a syndrome that describes the set of bits found to be in error.

Note: that this field is locked from the time that it is loaded up to the time when the error flag is

cleared by software. If the first error was a single bit, correctable error, then a subsequent multiple

bit error will overwrite this field. In all other cases, an error that occurs after the first error and

before the error flag has been cleared by software will escape recording.

3.7.20.

EAP – Error Address Pointer Register – Device #0

Address Offset:

8C-8Fh

Default Value:

0000_0000h

Access:

Read Only

Size:

32 bits

This register stores the DRAM address when an ECC error occurs.

Bit

Description

31:30

Reserved

29:1

Error Address Pointer (EAP): This field is used to store the 4-KB block of main memory of which

an error (single bit or multi-bit error) has occurred.

Note: that the value of this bit field represents the address of the first single or the first multiple bit

error occurrence after the error flag bits in the ERRSTS register have been cleared by software. A

multiple bit error will overwrite a single bit error. Once the error flag bits are set as a result of an error,

this bit field is locked and doesn’t change as a result of a new error.

Reserved

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