82845MP datasheet(48/157 Pages) INTEL

48 / 157 page

Intel

®82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

3.6.6.

RCVENSTR – Strength Control Register for RCVENOUT#

Signals

Address Offset:

34h

Default Value:

00h

Access:

Read Only, Read/Write

Size:

8 bits

This register controls the drive strength of the I/O buffers for the Receive Enable Out (RCVENOUT#)

signal.

Bit

Descriptions

7:3

Reserved

2:0

RCVEnOut# Strength Control: Sets drive strength as shown below:

000 = 0.75 X (default)

001 = 1.00 X

010 = 1.25 X

011 = 1.50 X

100 = 2.00 X

101 = 2.50 X

110 = 3.00 X

111 = 4.00 X

3.7.

Host-Hub Interface Bridge Device Registers – Device

Table 20 shows the access attributes for the configuration space. An “s” in the Default Value field means

that a strap determines the power-up default value for that bit. Table 21 below summarizes the MCH-M

configuration space for Device #0.

Table 20. Nomenclature for Access Attributes

Read Only. If a register is read only, writes to this register have no effect.

R/W

Read/Write. A register with this attribute can be read and written.

R/W/L

Read/Write/Lock A register with this attribute can be read, written, and Lock.

R/WC

Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1

clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

R/WO

Read/Write Once. A register bit with this attribute can be written to only once after power up. After the

first write, the bit becomes read only.

Lock. A register bit with this attribute becomes Read Only after a lock bit is set.

82845MP Datasheet(PDF) 48 Page - Intel Corporation

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