82845MP datasheet(5/157 Pages) INTEL

5 / 157 page

Intel

® 82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.8.17.

MBASE1 – Memory Base Address Register – Device #1 ........................... 96

3.8.18.

MLIMIT1 – Memory Limit Address Register – Device #1............................ 97

3.8.19.

PMBASE1 – Prefetchable Memory Base Address Register – Device #1 ... 98

3.8.20.

PMLIMIT1 – Prefetchable Memory Limit Address Register – Device #1 .... 99

3.8.21.

BCTRL1 – PCI-PCI Bridge Control Register – Device #1......................... 100

3.8.22.

ERRCMD1 – Error Command Register – Device #1 ................................ 101

3.8.23.

DWTMC – DRAM Write Thermal Management Control ........................... 102

3.8.24.

DRTMC – DRAM Read Thermal Management Control ............................ 104

System Address Map ............................................................................................................... 105

4.1.

Memory Address Ranges............................................................................................ 105

4.1.1.

VGA and MDA Memory Space.................................................................. 106

4.1.2.

PAM Memory Spaces................................................................................ 107

4.1.3.

ISA Hole Memory Space ........................................................................... 108

4.1.4.

TSEG SMM Memory Space ...................................................................... 108

4.1.5.

System Bus Interrupt APIC Memory Space .............................................. 109

4.1.6.

High SMM Memory Space ........................................................................ 109

4.1.7.

AGP Aperture Space (Device #0 BAR) ..................................................... 109

4.1.8.

AGP Memory and Prefetchable Memory................................................... 109

4.1.9.

Hub Interface A Subtractive Decode......................................................... 110

4.2.

AGP Memory Address Ranges ................................................................................... 110

4.2.1.

AGP DRAM Graphics Aperture................................................................. 110

4.3.

System Management Mode (SMM) Memory Range ................................................... 111

4.3.1.

SMM Space Definition............................................................................... 111

4.3.2.

SMM Space Restrictions ........................................................................... 112

4.4.

I/O Address Space ...................................................................................................... 112

4.5.

MCH-M Decode Rules and Cross-Bridge Address Mapping ...................................... 112

4.5.1.

Decode Rules for the Hub Interface A ...................................................... 112

4.5.2.

AGP Interface Decode Rules .................................................................... 113

Functional Description.............................................................................................................. 114

5.1.

Host Interface Overview .............................................................................................. 114

5.1.1.

Dynamic Bus Inversion.............................................................................. 114

5.1.2.

System Bus Interrupt Delivery................................................................... 114

5.1.3.

Upstream Interrupt Messages................................................................... 115

5.2.

System Memory Interface ........................................................................................... 115

5.2.1.

DDR Interface Overview............................................................................ 115

5.2.2.

Memory Organization and Configuration................................................... 116

5.2.2.1.

Configuration Mechanism for SO-DIMMs..................................... 116

5.2.2.1.1.

Memory Detection and Initialization............................ 116

5.2.2.1.2.

SMBus Configuration and Access of the Serial

Presence Detect Ports................................................ 116

5.2.2.1.3.

Memory Register Programming ................................. 116

5.2.3.

DRAM Performance Description ............................................................... 117

5.2.3.1.

Data Integrity (ECC) ..................................................................... 117

5.3.

AGP Interface Overview.............................................................................................. 117

5.3.1.

AGP Target Operations............................................................................. 118

5.3.2.

AGP Transaction Ordering........................................................................ 119

5.3.3.

AGP Signal Levels .................................................................................... 119

5.3.4.

4x AGP Protocol........................................................................................ 119

5.3.5.

Fast Writes ................................................................................................ 119

5.3.6.

AGP FRAME# Transactions on AGP........................................................ 120

82845MP Datasheet(PDF) 5 Page - Intel Corporation

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