22

Am386SX/SXL/SXLV Microprocessors Data Sheet

FINAL

CLK2

Reset

CLK (Internal)

BUSY

ADS

NA

D15–D0

BHE, BLE, W/R,

M/IO, HLDA

READY

Low

High

High

During Reset

During Reset

During Reset

Up to 30 CLK2

Up to 30 CLK2

Up to 30 CLK2

Reset

Cycle 1

Non-Pipelined

(Read)

1

2

3

17

18

19

395 396 397 398

2

11

2

1

2

1

2

T1

T2

Valid 1

Valid 1

(Note 1)

Low to begin self-test (Note 2)

Approximately

No self-test

ERROR

**

*

*

*

16305C–009

2

φ

φ

φφ

φφ

φφ

φ

SMI

Notes:

1. BUSY should be held stable for eight CLK2 periods before and after the CLK2 period in which the RESET falling edge

occurs.

2. If self-test is requested, the Am386SXLV microprocessor outputs remain in their reset state as shown here.

A23–A1,

D/C, LOCK

Figure 11. Bus Activity from Reset Until First Code Fetch (Am386SXLV Only)

≥ 15 CLK2 duration if not

going to request self-test.

≥ 80 CLK2 duration before

requesting self-test.

If self-test is performed, add

Internal Initialization

Negated to allow sensing of a

387DX math coprocessor

Asserted to indicate 387DX

math coprocessor protocol

(Floating)