16

Am386SX/SXL/SXLV Microprocessors Data Sheet

FINAL

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges at 33 MHz

Symbol

Parameter Description

Notes

Ref.

Figures

Final

Unit

Min

Max

Operating Frequency: Am386SX CPU

Am386SXL CPU

Half CLK2 freq.

Half CLK2 freq.

2

0

33

33

MHz

1

CLK2 Period

415

ns

2a

CLK2 High Time

at 2 V

4

6.25

ns

2b

CLK2 High Time

at 3.7 V

4

4

ns

3a

CLK2 Low Time

at 2 V

4

6.25

ns

3b

CLK2 Low Time

at 0.8 V

4

4.5

ns

4

CLK2 Fall Time

3.7 V to 0.8 V

(Note 3)

4

4

ns

5

CLK2 Rise Time

0.8 V to 3.7 V

(Note 3)

4

4

ns

6

A23–A1 Valid Delay

8

4

15

ns

7

A23–A1 Float Delay

(Note 1)

15

4

20

ns

8BHE, BLE, LOCK Valid Delay

8

4

15

ns

9BHE, BLE, LOCK Float Delay

(Note 1)

15

4

20

ns

10

M/IO, D/C, W/R, ADS Valid Delay

8

4

15

ns

11

W/R, M/IO, D/C, ADS Float Delay

(Note 1)

15

4

20

ns

12

D15–D0 Write Data Valid Delay

8

7

23

ns

12a

D15–D0 Write Data Hold Time

10

2

ns

13

D15–D0 Write Data Float Delay

(Note 1)

15

4

17

ns

14

HLDA Valid Delay

8

4

20

ns

14f

HLDA Float Delay

15

4

20

ns

15

NA Setup Time

75

ns

16

NA Hold Time

72

ns

19

READY Setup Time

7

7

ns

20

READY Hold Time

7

4

ns

21

D15–D0 Read Data Setup Time

7

5

ns

22

D15–D0 Read Data Hold Time

7

3

ns

23

HOLD Setup Time

7

9

ns

24

HOLD Hold Time

7

2

ns

25

RESET Setup Time

17

5

ns

26

RESET Hold Time

17

2

ns

27

NMI, INTR Setup Time

(Note 2)

7

5

ns

28

NMI, INTR Hold Time

(Note 2)

7

5

ns

29

PEREQ, ERROR, BUSY Setup Time

(Note 2)

7

5

ns

30

PEREQ, ERROR, BUSY Hold Time

(Note 2)

7

4

ns

Notes:

2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to

assure recognition within a specific CLK2 period.

3. Rise and Fall times are not tested. They are guaranteed by design characterization.

4. Min time is not 100% tested.