FINAL

Am386SX/SXL/SXLV Microprocessors Data Sheet

15

SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges

at 25 MHz

Symbol

Parameter Description

Notes

Ref.

Figures

Final

Unit

Min

Max

Operating Frequency: Am386SX CPU

Am386SXL/SXLV CPU

Half CLK2 freq.

Half CLK2 freq.

2

0

25

25

MHz

1

CLK2 Period

3, 4

20

ns

2

CLK2 High Time:

Am386SXLV CPU

34

ns

2a

CLK2 High Time:

Am386SX/SXL CPU

at 2 V

4

7

ns

2b

CLK2 High Time:

Am386SX/SXL CPU

4

4

ns

3

CLK2 Low Time:

Am386SXLV CPU

at 0.8 V

3

5

ns

3a

CLK2 Low Time:

Am386SX/SXL CPU

at 2 V

4

7

ns

3b

CLK2 Low Time:

Am386SX/SXL CPU

at 0.8 V

4

5

ns

4

CLK2 Fall Time:

Am386SX/SXL CPU

Am386SXLV CPU

2.4 V to 0.8 V

(Note 3)

4

3

7ns

5

CLK2 Rise Time:

Am386SX/SXL CPU

Am386SXLV CPU

0.8 V to 2.4 V

(Note 3)

4

3

7ns

6

A23–A1 Valid Delay

8

4

17

ns

7

A23–A1 Float Delay

(Note 1)

15

4

30

ns

8BHE, BLE, LOCK Valid Delay

8

4

17

ns

9BHE, BLE, LOCK Float Delay

(Note 1)

15

4

30

ns

10

M/IO, D/C, W/R, ADS Valid Delay

8

4

17

ns

10s

SMIADS Valid Delay

(Note 5)

8

4

25

ns

11

W/R, M/IO, D/C, ADS Float Delay

(Note 1)

15, 18

4

30

ns

11s

SMIADS Float Delay

(Notes 1, 5)

15

4

30

ns

12

D15–D0 Write Data Valid Delay

8, 9

7

23

ns

12a

D15–D0 Write Data Hold Time

10

2

ns

13

D15–D0 Write Data Float Delay

(Note 1)

15

4

22

ns

14

HLDA Valid Delay

8

4

22

ns

14f

HLDA Float Delay:

Am386SX/SXL

Am386SXLV

(Notes 1, 4)

15, 16

4

4

22

30

ns

15

NA Setup Time

75

ns

16

NA Hold Time

73

ns

19

READY Setup Time

7

9

ns

19s

SMIRDY Setup Time

(Note 5)

7

9

ns

20

READY Hold Time

7

4

ns

20s

SMIRDY Hold Time

(Note 5)

7

4

ns

21

D15–D0 Read Data Setup Time

7

7

ns

22

D15–D0 Read Data Hold Time

7

5

ns

23

HOLD Setup Time

7

9

ns

24

HOLD Hold Time

7

3

ns

25

RESET Setup Time

17

8

ns

26

RESET Hold Time

17

3

ns

27

NMI, INTR Setup Time

(Note 2)

7

6

ns

27s

SMI Setup Time

(Note 5)

7

6

ns

28

NMI, INTR Hold Time

(Note 2)

7

6

ns

28s

SMI Hold Time

(Note 5)

7

4

ns

29

(Note 2)

7

6

ns

30

(Note 2)

7

5

ns

31

SMI Valid Delay

(Note 5)

8, 15

4

22

ns

32

SMI Float Delay

(Notes 1, 4, 5)

16

4

30

ns

Notes:

2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to

assure recognition within a specific CLK2 period.

3. Rise and Fall times are not tested. They are guaranteed by design characterization.

4. Only during FLT assertion.

5. On Am386SXLV only.