FINAL

Am386SX/SXL/SXLV Microprocessors Data Sheet

23

CLK2

Control

Data

Address

Reset

Valid

Valid

Valid

FLT

Figure 12. Entering and Exiting FLT (Am386SXLV Only)

SMI

16306B–008

φ 1

φ 1

φ 1

φ 1

φ 1

φ 1

φ 1

φ 1

φ 1

φ 1

Valid

CLK2

SMI

SMIADS

φ 1

φ 1

φ 1

φ 1

φ 1

φ 1

φ 1

SMM in progress

Drive released by CPU

System may initiate another

SMI when necessary*

*Once initiated, the system must hold SMI Low until the first SMIADS. At this time, the system cannot drive SMI until three

CLK2 cycles after the CPU drives SMI High. (The CPU will drive SMI High for two CLK2 cycles. The additional clock allows

the CPU to completely release SMI and prevents any driver overlap.)

CPU driving SMI

System control of SMI

16306B–011

Figure 13. Initiating and Exiting SMM (Am386SXLV Only)

CLK2

SMI

RESET

φ 2

φ 2

SMM in progress

CPU drives SMI High for two CLK2 cycles 6–8

clocks after RESET is asserted.

16306B–010

Figure 14. RESET and SMI (Am386SXLV Only)