AM386SX datasheet(5/30 Pages) AMD

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Am386SX/SXL/SXLV Microprocessors Data Sheet

Description of SMM Operation

(Am386SXLV Only)

The execution of a System Management Interrupt has

four distinct phases: the initiation of the interrupt via

SMI, a processor state save, execution of the SMM in-

terrupt code, and a processor state restore (to resume

normal operation).

Interrupt Initiation

A System Management Interrupt is initiated by the driv-

ing of a synchronous, active Low pulse on the SMI pin

until the first SMIADS is asserted. This pulse period will

ensure recognition of the interrupt. The CPU drives the

SMI pin active after the completion of the current oper-

ation (active bus cycle, instruction execution, or both).

The active drive of the pin by the CPU is released at the

end of the interrupt routine following the last register

read of the saved state. The CPU drives SMI High for

two CLK2 cycles prior to releasing the drive of SMI.

An SMI cannot be masked off by the CPU, and it will al-

ways be recognized by the CPU, regardless of operat-

ing modes. This includes the Real, Protected, and Vir-

tual-8086 modes of the processor.

While the CPU is in SMM, a bus hold request via the

HOLD pin is granted. The HLDA pin goes active after

bus release and the SMIADS pin floats along with the

other pins that normally float during a bus hold cycle.

SMI does not float during a Bus Hold cycle.

Processor State Save

The first set of SMM bus transfer cycles after the CPU’s

recognition of an active SMI is the processor saving its

state to an external RAM array in a separate address

space from main system memory. This is accom-

plished by using the SMIADS and SMIRDY pins for ini-

tiation and termination of bus cycles, instead of the

ADS and READY pins. The 24-bit addresses to which

the CPU saves its state are 60000h–600CBh and

60100h–60127h. These are fixed address locations for

each register saved.

To ensure valid operation, pipelining must be disabled

while the processor is in SMM. There are 114 data

transfer cycles.

SMI Code Execution

After the processor state is saved to the separate SMM

memory space, the execution of the SMM interrupt rou-

tine code begins. The processor enters Real mode,

sets most of the register values to “reset” values (those

values normally seen after a CPU reset), and begins

fetching code from address FFFFF0h in the separate

SMM memory space. Normally, the first thing the inter-

rupt routine code does is a FAR JUMP to the Real

mode entry point for the SMM interrupt routine, which

is also in SMM memory space.

Both INTR and NMI are disabled upon entry into SMM.

The SMM code can be located anywhere within the

1-Mbyte Real mode address space, except for where

the processor state is saved. I/O cycles, as a result of

the IN, OUT, INS, and OUTS instructions, will go to the

normal address space, utilizing the normal ADS and

READY bus interface signals. This facilitates power

management code manipulating system hardware reg-

isters as needed through the standard I/O subsystem;

a separate I/O space is not implemented.

Processor State Restore

(Resuming Normal Execution)

Returning to normal code execution in the main system

memory, including restoring the processor operating

mode, is accomplished by executing a special code se-

quence. This code invokes a restore CPU state opera-

tion that reloads the CPU registers from the saved data

in the RAM controlled by SMIADS and SMIRDY.

The ES:EDI register pair must point to the physical ad-

dress of the processor save state (6000h). In Real

mode the address is calculated as ES•16 + EDI offset.

The saved state should not cross a 64K boundary. The

RES3 instruction (0F 07) should be executed to start

the restore state operation. After completion of the re-

store state operation, the SMI pin will be deactivated by

the CPU and normal code execution will continue at the

point where it left off before the SMI occurred. There

are 114 data transfer cycles in the restore operation.

Software Features (Am386SXLV Only)

Several features of the SMI function provide support for

special operations during the execution of the system’s

software. These features involve the execution of re-

served opcodes to induce specific SMI-related opera-

tions.

Software SMI Generation

Besides hardware initiation of the SMI via the SMI pin,

there is also a software-induced SMI mechanism. Gen-

erating a soft SMI involves setting a control bit (Bit 12)

in the Debug Control Register (DR7) and executing an

SMI instruction (opcode F1h).

The functional sequence of the software-based SMI is

identical to the hardware-based SMI with the exception

that the SMI pin is not initially driven active by an exter-

nal source. Upon execution of a soft SMI opcode, the

SMI pin is driven active (Low) by the processor before

the save state operation begins.

Memory Transfers to Main System Memory

While executing an SMI routine, the interrupt code can

initiate memory data reads and writes to the main sys-

tem memory using the normal ADS and READY pins.

This initiation is accomplished by using reserved op-

codes that are special forms of the MOV instruction

(called UMOV). The UMOV opcodes can move byte,

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