AM386SX datasheet(11/30 Pages) AMD

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Am386SX/SXL/SXLV Microprocessors Data Sheet

READY

Bus Ready (Active Low; Input)

Terminates the bus cycle initiated by ADS.

RESET

Reset (Active High; Input)

Suspends any operation in progress and places the

Am386SX/SXL/SXLV microprocessor in a known reset

state.

SMI (Am386SXLV Only)

System Management Interrupt (Active Low; I/O)

A non-maskable interrupt pin that signals to the

Am386SXLV microprocessor to suspend execution

and enter System Management Mode. SMI has an in-

ternal pull-up resistor. SMI has a dynamic internal

pull-up resistor that is disabled when the processor is

in SMM. SMI is not three-stated during Hold Acknowl-

edge bus cycles.

SMIADS (Am386SXLV Only)

SMI Address Status (Active Low; Output)

When active, this pin indicates that a valid bus cycle

definition and address (W/R, D/C, M/IO, BHE, BLE,

and A23–A1) are being driven at the Am386SXLV mi-

croprocessor pins while in the System Management

mode. Bus cycles initiated by SMIADS must be termi-

nated by SMIRDY.

SMIRDY (Am386SXLV Only)

SMI Ready (Active Low; Input)

This input terminates the current bus cycle to the SMM

mode address space in the same manner the READY

pin does for the normal mode address space. SMIRDY

has an internal pull-up resistor. READY and SMIRDY

must not be tied together.

VCC

System Power (Input)

Provides the 5 V nominal DC supply input.

VSS

System Ground (Input)

Provides the 0-V connection from which all inputs and

outputs are measured.

W/R

Write/Read (Output)

A bus cycle definition pin that distinguishes write cycles

from read cycles.

LOGIC SYMBOL

HOLD

HLDA

ERROR

NMI

LOCK

INTR

PEREQ

READY

RESET

ADS

CLK2

D/C

D15–D0

BLE, BHE

A23–A1

M/IO

Bus Arbitration

Control

W/R

BUSY

Data Bus

Interrupt

Control

Math

Coprocessor

Control

Bus

Cycle

Definition

Bus

Cycle

Control

Address

Bus

2X Clock

16305C–003

FLT

Float

SMIRDY

System

Management

Control*

Mode

SMIADS

SMI

IIBEN

Am386SXLV

Microprocessor

*On Am386SXLV only

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