SLRC400 datasheet(24/101 Pages) NXP

24 / 101 page

SLRC400_33

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Product data sheet

PUBLIC

Rev. 3.3 — 23 March 2010

054333

24 of 101

NXP Semiconductors

SLRC400

ICODE reader IC

8.8 Oscillator circuit

The clock applied to the SLRC400 acts as a time basis for the synchronous system

encoder and decoder. The stability of the clock frequency is an important factor for correct

operation. To obtain highest performance, clock jitter must be as small as possible. This is

best achieved by using the internal oscillator buffer with the recommended circuitry.

If an external clock source is used, the clock signal must be applied to pin OSCIN. In this

case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock

quality has been verified. It must meet the specifications described in Section 12.4.4 on

page 84.

Remark: We do not recommend using an external clock source.

8.9 Transmitter pins TX1 and TX2

The signal on pins TX1 and TX2 is the 13.56 MHz carrier modulated by an envelope

signal. It can be used to drive an antenna directly, using minimal passive components for

matching and filtering (see Section 14.1 on page 85). To enable this, the output circuitry is

designed with a very low-impedance source resistance. The TxControl register is used to

control the TX1 and TX2 signals.

8.9.1 Configuring pins TX1 and TX2

TX1 pin configurations are described in Table 20.

TX2 pin configurations are described in Table 21.

Fig 9.

Quartz clock connection

Table 20.

Pin TX1 configurations

TxControl register

configuration

Envelope

TX1 signal

TX1RFEn

LOW (GND)

13.56 MHz modulated carrier

13.56 MHz unmodulated carrier

SLRC400 Datasheet(PDF) 24 Page - NXP Semiconductors