SLRC400 datasheet(12/101 Pages) NXP

12 / 101 page

SLRC400_33

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Product data sheet

PUBLIC

Rev. 3.3 — 23 March 2010

054333

12 of 101

NXP Semiconductors

SLRC400

ICODE reader IC

8.2.2.3 Register initialization file (read/write)

The EEPROM memory content from block address 3 to 7 can initialize register sub

addresses 10h to 2Fh when the LoadConfig command is executed (see Section 10.4.1 on

page 75). This command requires the EEPROM starting byte address as a two byte

argument for the initialization procedure.

The byte assignment is shown in Table 11.

The register initialization file is large enough to hold values for two initialization sets and

up to one block (16-byte) of user data.

Remark: The register initialization file can be read/written by users and these bytes can

be used to store other user data.

8.3 FIFO buffer

An 8

64 bit FIFO buffer is used in the SLRC400 to act as a parallel-to-parallel converter.

It buffers both the input and output data streams between the microprocessor and the

internal circuitry of the SLRC400. This makes it possible to manage data streams up to 64

bytes long without needing to take timing constraints into account.

8.3.1 Accessing the FIFO buffer

8.3.1.1 Access rules

The FIFO buffer input and output data bus is connected to the FIFOData register. Writing

to this register stores one byte in the FIFO buffer and increments the FIFO buffer write

pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO

buffer read pointer and increments the FIFO buffer read pointer. The distance between the

write and read pointer can be obtained by reading the FIFOLength register.

When the microprocessor starts a command, the SLRC400 can still access the FIFO

buffer while the command is running. Only one FIFO buffer has been implemented which

is used for input and output. Therefore, the microprocessor must ensure that there are no

inadvertent FIFO buffer accesses. Table 12 gives an overview of FIFO buffer access

during command processing.

Table 11.

Byte assignment for register initialization at StartUp

EEPROM byte address

Remark

EEPROM starting byte address

10h

skipped

EEPROM + 1 starting byte address

11h

copied

……

EEPROM + 31 starting byte address

2Fh

copied

Table 12.

FIFO buffer access

Active

command

FIFO buffer

Remark

P Write

P Read

StartUp

Idle

Transmit

yes

Receive

yes

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