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SLRC400 Datasheet(PDF) 8 Page - NXP Semiconductors

Part # SLRC400
Description  ICODE reader IC
PDF  101 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SLRC400 Datasheet(HTML) 8 Page - NXP Semiconductors

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SLRC400_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 23 March 2010
054333
8 of 101
NXP Semiconductors
SLRC400
ICODE reader IC
8.1.3.2 Common read and write strobe
Refer to Section 12.4.2 on page 81 for timing specification.
8.1.3.3 Common read and write strobe: EPP with handshake
Refer to Section 12.4.3 on page 82 for timing specification.
Remark: In the EPP standard a chip select signal is not defined. To cover this situation,
the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not
used, it is mandatory that pin NCS is connected to pin DVSS.
Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is
high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after
the reset phase. The SLRC400 does not support Read Address Cycle.
Fig 4.
Connection to microprocessor: common read and write strobes
Fig 5.
Connection to microprocessor: EPP common read/write strobes and handshake



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