SLRC400 datasheet(28/101 Pages) NXP

28 / 101 page

SLRC400_33

All information provided in this document is subject to legal disclaimers.

Product data sheet

PUBLIC

Rev. 3.3 — 23 March 2010

054333

28 of 101

NXP Semiconductors

SLRC400

ICODE reader IC

8.9.3.3 Calculating the relative source resistance

The reference source resistance RS(ref) can be calculated using Equation 6.

(6)

8.9.3.4 Calculating the effective source resistance

Wiring resistance (RS(wire)): Wiring and bonding add a constant offset to the driver

resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The

additional resistance for pin TX1 (RS(wire)TX1) can be set approximately as shown in

Equation 7.

(7)

Effective resistance (RSx): The source resistances of the driver transistors (RsMaxP

byte) read from the Product Information Field (see Section 8.2.1 on page 9) are measured

during the production test with CwConductance register’s GsCfgCW[5:0] = 01h.

To calculate the driver resistance for a specific value set in ModConductance register ‘s

GsCfgMod[5:0], use Equation 8.

(8)

8.9.4 Pulse width

The envelope carries the data signal information that is transmitted to the label. The data

signal is encoded using either 1 out of 256 RZ, or 1 out of 4 codes. In addition, each

pause of the encoded signal is again encoded as a pulse of a certain width. The width of

the pulse is adjusted using the ModWidth register. The pulse width (tw) is calculated using

Equation 9 where the clock frequency constant (fclk)= 13.56 MHz.

(9)

8.10 Receiver circuitry

The SLRC400 uses an integrated quadrature demodulation circuit which extracts the

subcarrier signal from the 13.56 MHz ASK-modulated signal on pin RX.

The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a

phase-shift of 90 between them. Both resulting subcarrier signals are amplified, filtered

and forwarded to the correlation circuitry. The correlation results are evaluated, digitized

and then passed to the digital circuitry. Various adjustments can be made to obtain

optimum performance for all processing units.

8.10.1 Receiver circuit block diagram

Figure 10 shows the block diagram of the receiver circuit. The receiving process can be

broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal

is performed. To achieve the optimum performance, automatic Q-clock calibration is

recommended (see Section 8.10.2.1 on page 29).

RSref

MANTGsCfgCW

------

EXPGsCfgCW

--------------------------------------------------------------------------------

RSwire TX1 500 m

RSx

RSref maxP RSwire TX1

–

RSrel

RSwire TX1

ModWidth 1

fclk

-------------------------------------

SLRC400 Datasheet(PDF) 28 Page - NXP Semiconductors

SLRC400 Datasheet(HTML) 28 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL