SLRC400 datasheet(13/101 Pages) NXP

13 / 101 page

SLRC400_33

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Product data sheet

PUBLIC

Rev. 3.3 — 23 March 2010

054333

13 of 101

NXP Semiconductors

SLRC400

ICODE reader IC

8.3.2 Controlling the FIFO buffer

In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be

reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit

FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO

buffer to be written with another 64 bytes of data.

8.3.3 FIFO buffer status information

The microprocessor can get the following FIFO buffer status data:

• the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0]

• the FIFO buffer full warning: bit HiAlert

• the FIFO buffer empty warning: bit LoAlert

• the FIFO buffer overflow warning: bit FIFOOvfl.

Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.

The SLRC400 can generate an interrupt signal when:

• bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated.

• bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated.

The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be

stored in the FIFO buffer. The trigger is generated by Equation 1:

(1)

The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or

less are stored in the FIFO buffer. The trigger is generated by Equation 2:

(2)

8.3.4 FIFO buffer registers and flags

Table 13 shows the related FIFO buffer flags in alphabetical order.

Transceive

yes

the microprocessor has to know the state of the

command (transmitting or receiving)

WriteE2

yes

ReadE2

yes

the microprocessor has to prepare the arguments,

afterwards only reading is allowed

LoadConfig

yes

CalcCRC

yes

Table 12.

FIFO buffer access

Active

command

FIFO buffer

Remark

P Write

P Read

HiAlert

64 FIFOLength

–

WaterLevel

LoAlert

FIFOLength WaterLevel

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