SLRC400 datasheet(34/101 Pages) NXP

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SLRC400_33

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Product data sheet

PUBLIC

Rev. 3.3 — 23 March 2010

054333

34 of 101

NXP Semiconductors

SLRC400

ICODE reader IC

9. SLRC400 registers

9.1 Register addressing modes

Three methods can be used to operate the SLRC400:

• initiating functions and controlling data by executing commands

• configuring the functional operation using a set of configuration bits

• monitoring the state of the SLRC400 by reading status flags

The commands, configuration bits and flags are accessed using the microprocessor

interface. The SLRC400 can internally address 64 registers using six address lines.

9.1.1 Page registers

The SLRC400 register set is segmented into eight pages containing eight registers each.

A Page register can always be addressed, irrespective of which page is currently

selected.

9.1.2 Dedicated address bus

When using the SLRC400 with the dedicated address bus, the microprocessor defines

three address lines using address pins A0, A1 and A2. This enables addressing within a

page. To switch between registers in different pages a paging mechanism needs to be

used.

Table 28 shows how the register address is assembled.

9.1.3 Multiplexed address bus

The microprocessor may define all six address lines at once using the SLRC400 with a

multiplexed address bus. In this case either the paging mechanism or linear addressing

can be used.

Table 29 shows how the register address is assembled.

9.2 Register bit behavior

Bits and flags for different registers behave differently, depending on their functions. In

principle, bits with same behavior are grouped in common registers. Table 30 describes

the function of the Access column in the register tables.

Table 28.

Dedicated address bus: assembling the register address

PageSelect2

PageSelect1

PageSelect0

A2 A1 A0

Table 29.

Multiplexed address bus: assembling the register address

Multiplexed

address bus

type

UsePage

Select

Paging mode

PageSelect2 PageSelect1 PageSelect0 AD2

AD1 AD0

Linear

addressing

AD5

AD4

AD3

AD2

AD1 AD0

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