M263 datasheet(318/398 Pages) NUVOTON

318 / 398 page

M261/M262/M263

Mar 25, 2020

Page 318 of 398

Rev 1.02

6.19

Serial Peripheral Interface (SPI)

6.19.1

Overview

The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full

duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The

M261/M262/M263 series contains up to four sets of SPI controllers performing a serial-to-parallel

conversion on data received from a peripheral device, and a parallel-to-serial conversion on data

transmitted to a peripheral device. Each SPI controller can be configured as a master or a slave

device and supports the PDMA function to access the data buffer. Each SPI controller also supports

I2S mode to connect external audio CODEC.

6.19.2

Features



SPI Mode

–

Up to four sets of SPI controllers

–

Supports Master or Slave mode operation

–

Configurable bit length of a transaction word from 8 to 32-bit

–

Provides separate 4-level depth transmit and receive FIFO buffers

–

Supports MSB first or LSB first transfer sequence

–

Supports Byte Reorder function

–

Supports Byte or Word Suspend mode

–

Supports PDMA transfer

–

Supports one data channel half-duplex transfer

–

Supports receive-only mode



2S Mode

–

Supports Master or Slave

–

Capable of handling 8-, 16-, 24- and 32-bit word sizes

–

Each provides two 4-level FIFO data buffers, one for transmitting and the other for

receiving

–

Supports monaural and stereo audio data

–

Supports PCM mode A, PCM mode B, I

2S and MSB justified data format

–

Supports two PDMA requests, one for transmitting and the other for receiving

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