M263 datasheet(280/398 Pages) NUVOTON

280 / 398 page

M261/M262/M263

Mar 25, 2020

Page 280 of 398

Rev 1.02

6.2.5

Bus Matrix

PDMA1

Crypto

Cortex-M23

PDMA0

FLASH

SRAM0

(32 KB)

SRAM1

(64 KB)

APB0

Peripheral

APB1

Peripheral

EBI

AHB

Peripheral

SDH0

USBH

Figure 6.2-2 M261 Bus Martix Architecture Diagram

Refer to Figure 6.2-2. This chip uses Advanced Microcontroller Bus Architecture (AMBA) protocol to

implement system bus. The system has five masters and seven slaves, in which a different master

can communicate with a different slave at the same time through Bus Matrix. The Cortex

® -M23 core

processor acts as the master in Bus Matrix, located on M0 to communicate with any slaves through

Bus Matrix. PDMA0 and PDMA1 are Peripheral Direct Memory Access and act as the master in Bus

Matrix, respectively located on M1 and M4, which can communicate with any slaves through Bus

Matrix. SDH0 and Crypto share the same master bandwidth located on M2. USBH acts as the master

role in Bus Matrix and is located on M3. The slave AHB Peripheral is the Advanced High-performance

Bus (AHB) controller, and any master can communicate with any AHB peripheral through Bus Matrix.

6.2.6

System Memory Map

This chip provides 4G-byte addressing space. The memory locations assigned to each on-chip

controllers are shown in Table 6.2-7. The detailed register definition, memory space, and

programming will be described in the following sections for each on-chip peripheral. The NuMicro

M261/M262/M263 series only supports little-endian data format.

Address Space

Token

Controllers

Flash and SRAM Memory Space

0x0000_0000

– 0x0007_FFFF

FLASH_BA

FLASH Memory Space (512 KB)

0x2000_0000

– 0x2000_7FFF

SRAM0_BA

SRAM Memory Space (32 KB)

0x2000_8000

– 0x2001_7FFF

SRAM1_BA

SRAM Memory Space (64 KB)

0x6000_0000

– 0x6FFF_FFFF

EXTMEM_BA

External Memory Space (256 MB)

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