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M263 Datasheet(PDF) 284 Page - Nuvoton Technology Corporation |
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M263 Datasheet(HTML) 284 Page - Nuvoton Technology Corporation |
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284 / 398 page  M261/M262/M263 Mar 25, 2020 Page 284 of 398 Rev 1.02 32 Kbytes SRAM bank0 0x2000_0000 Reserved 0x2FFF_FFFF 64 Kbytes SRAM bank1 0x2000_7FFF 0x2001_7FFF 0x2000_8000 0x2001_8000 96 Kbytes device Figure 6.2-9 SRAM Memory Organization SRAM bank0 has byte parity error check function. When CPU is accessing SRAM bank0, the parity error checking mechanism is dynamic operating. As parity error occurs, the PERRIF (SYS_SRAMSTS[0]) will be asserted to 1 and the SYS_SRAMEADR register will recode the address with the parity error. Chip will enter interrupt when SRAM parity error occurs if PERRIEN (SYS_SRAMICTL[0]) is set to 1. When SRAM parity error occurs, chip will stop detecting SRAM parity error until user writes 1 to clear the PERRIF(SYS_SRAMSTS[0]) bit. |
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