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M263 Datasheet(PDF) 285 Page - Nuvoton Technology Corporation |
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M263 Datasheet(HTML) 285 Page - Nuvoton Technology Corporation |
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285 / 398 page ![]() M261/M262/M263 Mar 25, 2020 Page 285 of 398 Rev 1.02 SRAM Power Control SRAM bank0 and bank1 have marco retention and power shut down function. Each SRAM marco can be configured to retention or power shut down mode independently by SRAMxPMn (SYS_SRAMPCTL[23:8], x=0-1 n=0-3). When chip entering power-down, each SRAM marco will enter retention or power shut down or keep operation mode depending on SRAMxPMn(SYS_SRAMPCTL[23:8], x=0-1 n=0-3).When chip power down wake up, SRAM marco will wake up from retention or power shut down mode. User must identify which SRAM marco that CPU first accessed for saving power down wake up time by STACK(SYS_SRAMPCTL[1:0]). Figure 6.2-10 shows the SRAM marco number in bank0 and bank1. When chip power down wake up, the first wake up SRAM marco is depened on STACK (SYS_SRAMPCTL[1:0]), the rest SRAM marcos wake up in the order of marco number, from SRAM marco0 to SRAM marco7. 0x2000_0000 0x2000_4000 0x2000_8000 0x2000_6000 0x2000_C000 96 Kbytes device 16 Kbytes SRAM Marco 7 16 Kbytes SRAM Marco 6 16 Kbytes SRAM Marco 5 16 Kbytes SRAM Marco 4 8 Kbytes SRAM Marco 3 8 Kbytes SRAM Marco 2 8 Kbytes SRAM Marco 1 8K byte SRAM Marco 0 0x2000_2000 0x2001_0000 0x2001_4000 0x2001_7FFF Figure 6.2-10 SRAM Marco Organization 6.2.8 Auto Trim This chip supports auto-trim function: the HIRC trim (12 MHz RC oscillator, 48 MHz RC oscillator), according to the accurate external 32.768 kHz crystal oscillator or internal USB synchronous mode, to automatically get accurate HIRC output frequency, 0.25 % deviation within all temperature ranges. For instance, the system needs an accurate 12 MHz clock. In such case, if neither using PLL as the system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL (SYS_TCTL12M[10] reference clock selection) to “1”, set FREQSEL (SYS_TCTL12M[1:0] trim frequency selec tion) to “01”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK |
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