M263 datasheet(286/398 Pages) NUVOTON

286 / 398 page

M261/M262/M263

Mar 25, 2020

Page 286 of 398

Rev 1.02

(SYS_TISTS12M[8

] HIRC frequency lock status) “1” indicates the HIRC output frequency is accurate

within 0.25% deviation.

In another case, the system needs an accurate 48 MHz clock. In such case, if neither using PLL as

the system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL

(SYS_TCTL48M[10] reference clock selection) to

“1”, set FREQSEL (SYS_TCTL48M[1:0] trim

frequency selection) to

“01”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK

(SYS_TISTS48M[8] HIRC48

frequency lock status) “1” indicates the HIRC output frequency is

accurate within 0.25% deviation.

6.2.9

System Timer (SysTick)

The Cortex

® -M23 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-

on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be

used as a Real Time Operating System (RTOS) tick timer or as a simple counter.

When system timer is enabled, it will count down from the value in the SysTick Current Value Register

(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register

(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter

transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.

The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero

before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than

an arbitrary value when it is enabled.

If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded

with this value. This mechanism can be used to disable the feature independently from the timer

enable bit.

For more detailed information, please refer to the “Arm

® Cortex® -M23 Technical Reference Manual”

and “Arm

® v8-M Architecture Reference Manual”.

6.2.10

Nested Vectored Interrupt Controller (NVIC)

The NVIC and the processor core interface are closely coupled to enable low latency interrupt

processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the

stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC

from privileged mode, but you can cause interrupts to enter a pending state in user mode if you enable

the Configuration and Control Register. Any other user mode access causes a bus fault. You can

access all NVIC registers using byte, halfword, and word accesses unless otherwise stated. NVIC

registers are located within the SCS (System Control Space). All NVIC registers and system debug

registers are little-endian regardless of the endianness state of the processor.

The NVIC supports:



An implementation-defined number of interrupts, in the range 1-240 interrupts.



A programmable priority level of 0-3 for each interrupt; a higher level corresponds to a

lower priority, so level 0 is the highest interrupt priority.



Level and pulse detection of interrupt signals.



Dynamic reprioritization of interrupts.



Grouping of priority values into group priority and subpriority fields.



Interrupt tail-chaining.



An external Non Maskable Interrupt (NMI)



WIC with Ultra-low Power Sleep mode support

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