M263 datasheet(290/398 Pages) NUVOTON

290 / 398 page

M261/M262/M263

Mar 25, 2020

Page 290 of 398

Rev 1.02

UART4_INT

UART4 interrupt

UART5_INT

UART5 interrupt

USCI0_INT

USCI0 interrupt

USCI1_INT

USCI1 interrupt

BPWM0_INT

BPWM0 interrupt

BPWM1_INT

BPWM1 interrupt

Reserved

I2C2_INT

I2C2 interrupt

Reserved

100

QEI0_INT

QEI0 interrupt

101

QEI1_INT

QEI1 interrupt

102

ECAP0_INT

ECAP0 interrupt

103

ECAP1_INT

ECAP1 interrupt

104

GPH_INT

External interrupt from PH[15:0] pin

105

EINT7

External interrupt from PB.9 or PD.10 pins

106

Reserved

107

Reserved

108

Reserved

109

Reserved

110

Reserved

111

Reserved

114

PDMA1_INT

PDMA 1 interrupt

115

Reserved

116

100

Reserved

117

101

TRNG_INT

TRNG interrupt

Table 6.2-9 Interrupt Number Table

6.2.10.2

Operation Description

NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or

Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear

policy, both registers reading back the current enabled state of the corresponding interrupts. When an

interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the

interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until

cleared by reset or an exception return. Clearing the enable bit prevents new activations of the

associated interrupt.

NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to

enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register

M263 Datasheet(PDF) 290 Page - Nuvoton Technology Corporation

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