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M263 Datasheet(PDF) 291 Page - Nuvoton Technology Corporation |
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M263 Datasheet(HTML) 291 Page - Nuvoton Technology Corporation |
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291 / 398 page ![]() M261/M262/M263 Mar 25, 2020 Page 291 of 398 Rev 1.02 respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts). The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section. |
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