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M263 Datasheet(PDF) 292 Page - Nuvoton Technology Corporation |
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M263 Datasheet(HTML) 292 Page - Nuvoton Technology Corporation |
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292 / 398 page ![]() M261/M262/M263 Mar 25, 2020 Page 292 of 398 Rev 1.02 6.3 Clock Controller 6.3.1 Overview The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode until CPU sets the Power-down enable bit PDEN (CLK_PWRCTL[7]) and core executes the WFI instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 4~24 MHz external high speed crystal (HXT), 48 MHz internal high speed RC oscillator (HIRC48) and 12 MHz internal high speed RC oscillator (HIRC) to reduce the overall system power consumption. Figure 6.3-1 to Figure 6.3-3 show the clock generator and the overview of the clock source control. |
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