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M263 Datasheet(PDF) 294 Page - Nuvoton Technology Corporation |
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M263 Datasheet(HTML) 294 Page - Nuvoton Technology Corporation |
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294 / 398 page  M261/M262/M263 Mar 25, 2020 Page 294 of 398 Rev 1.02 TMR 0 TMR 1 111 010 001 000 PCLK0 32.768 kHz 4~24 MHz 12 MHz CLK_CLKSEL1 [10: 8] CLK_CLKSEL1 [14:12] 101 10 kHz 011 TM0~TM1 HXT LXT TM0/TM1 HIRC PCLK0 LIRC TMR 2 TMR 3 111 010 001 000 CLK_CLKSEL1 [18:16] CLK_CLKSEL1 [22:20] 101 011 TM2~TM3 TM2/TM3 UART 0 1/(UART0DIV+1) 11 10 01 00 4~24 MHz HXT 32.768 kHz LXT PCLK1 PCLK1 10 kHz LIRC 12 MHz HIRC 4~24 MHz HXT PLLFOUT PLL 32.768 kHz LXT 12 MHz HIRC CLK_CLKSEL1[25:24] CLK_CLKSEL1[27:26] HCLK 4~24 MHz 12 MHz 32.768 kHz CLK_CLKSEL1[29:28] 11 10 01 00 Clock Output HXT LXT HIRC HCLK EPWM 0 PCLK0 SPI1 PCLK0 4~24 MHz 12 MHz PLLFOUT CLK_CLKSEL2[3:2] CLK_CLKSEL2[7:6] CLK_CLKSEL2[13:12] 11 10 01 00 QSPI0 SPI3 SPI2 PCLK1 4~24 MHz 12 MHz PLLFOUT CLK_CLKSEL2[5:4] CLK_CLKSEL2[11:10] 11 10 01 00 SPI0 HIRC PCLK0 PLLFOUT HXT HIRC PCLK1 PLLFOUT HXT UART 1 1/(UART1DIV+1) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. SC0 PCLK0 4~24 MHz 12 MHz PLLFOUT CLK_CLKSEL3[1:0] 11 10 01 00 1/(SC0DIV+1) HIRC PCLK0 PLL HXT CLK_CLKSEL3[5:4] SC2 1/(SC2DIV+1) SC1 PCLK1 4~24 MHz 12 MHz PLLFOUT CLK_CLKSEL3[3:2] 11 10 01 00 1/(SC1DIV+1) HIRC PCLK1 PLL HXT EPWM 1 PCLK1 BPWM 0 PCLK0 BPWM 1 PCLK1 UART 2 1/(UART2DIV+1) 11 10 01 00 4~24 MHz HXT PLLFOUT PLL 32.768 kHz LXT 12 MHz HIRC CLK_CLKSEL3[25:24] CLK_CLKSEL3[27:26] UART 3 1/(UART3DIV+1) CLK_CLKSEL3[29:28] CLK_CLKSEL3[31:30] UART 4 1/(UART4DIV+1) UART 5 1/(UART5DIV+1) Figure 6.3-2 Clock Generator Global View Diagram (2/3) |
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