M263 datasheet(283/398 Pages) NUVOTON

283 / 398 page

M261/M262/M263

Mar 25, 2020

Page 283 of 398

Rev 1.02

6.2.7

SRAM Memory Orginization

This chip supports embedded SRAM with a total of 96 Kbytes size and the SRAM organization is

separated into two banks: SRAM bank0 and SRAM bank1. The first bank has 32 Kbytes address

space and the second bank has 64Kbyte address space. These two banks address space can be

accessed simultaneously. The SRAM bank0 supports parity error check to make sure the chip is

operating more stable.



Supports total 96 Kbytes SRAM



Supports byte / half word / word write



Supports fixed 32 Kbytes SRAM bank0 for independent access



Supports parity error check function for SRAM bank0



Supports oversize response error

AHB interface

controller

SRAM decoder

SRAM bank0

SRAM bank1

SRAM decoder

AHB interface

controller

Figure 6.2-8 SRAM Block Diagram

Figure 6.2-9 shows the SRAM organization. There are two SRAM banks. The bank0 is addressed to

32 Kbytes and the bank1 is addressed to 64 Kbytes. The bank0 address space is from 0x2000_0000

to 0x2000_7FFF. The bank1 address space is from 0x2000_8000 to 0x2001_7FFF. The address

between 0x2001_8000 to 0x2FFF_FFFF is illegal memory space and chip will enter hardfault if CPU

accesses these illegal memory addresses.

M263 Datasheet(PDF) 283 Page - Nuvoton Technology Corporation