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ATTINY412 Datasheet(PDF) 65 Page - Microchip Technology |
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ATTINY412 Datasheet(HTML) 65 Page - Microchip Technology |
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65 / 479 page ![]() 10.5.3 Main Clock Lock Name: MCLKLOCK Offset: 0x02 Reset: 0x00 Property: Configuration Change Protection Bit 7 6 5 4 3 2 1 0 LOCKEN Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 x Bit 0 – LOCKEN: Lock Enable Writing this bit to '1' will lock the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers, and, if applicable, the calibration settings for the current Main Clock source from further software updates. Once locked, the CLKCTRL.MCLKLOCK registers cannot be accessed until the next hardware Reset. This provides protection for the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers and calibration settings for the Main Clock source from unintentional modification by software. Related Links FUSES - Configuration and User Fuses 10.5.4 Main Clock Status Name: MCLKSTATUS Offset: 0x03 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 EXTS XOSC32KS OSC32KS OSC20MS SOSC Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 – EXTS: External Clock Status Value Description 0 EXTCLK has not started 1 EXTCLK has started Bit 6 – XOSC32KS: XOSC32K Status The status bit will only be available if the source is requested as the main clock or by another module. If the oscillators RUNSTDBY bit is set but the oscillator is unused/not requested this bit will be 0. Value Description 0 XOSC32K is not stable 1 XOSC32K is stable ATtiny212/412 © 2017 Microchip Technology Inc. Datasheet Preliminary DS40001911A-page 65 |
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