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LAN9514 Datasheet(PDF) 44 Page - Microchip Technology |
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LAN9514 Datasheet(HTML) 44 Page - Microchip Technology |
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44 / 54 page  LAN9514/LAN9514I DS00002306A-page 44 2009-2016 Microchip Technology Inc. 4.5.4 JTAG TIMING This section specifies the JTAG timing of the device. TABLE 4-8: EEPROM TIMING VALUES Symbol Description Min TYP Max Units tckcyc EECLK Cycle time 1110 — 1130 ns tckh EECLK High time 550 — 570 ns tckl EECLK Low time 550 — 570 ns tcshckh EECS high before rising edge of EECLK 1070 — — ns tcklcsl EECLK falling edge to EECS low 30 — — ns tdvckh EEDO valid before rising edge of EECLK 550 — — ns tckhdis EEDO disable after rising edge EECLK 550 — — ns tdsckh EEDI setup to rising edge of EECLK 90 — — ns tdhckh EEDI hold after rising edge of EECLK 0 — — ns tckldis EECLK low to data disable (OUTPUT) 580 — — ns tcshdv EEDIO valid after EECS high (VERIFY) — — 600 ns tdhcsl EEDIO hold after EECS low (VERIFY) 0 — — ns tcsl EECS low 1070 — — ns FIGURE 4-3: JTAG TIMING TCK (Input) TDI, TMS (Inputs) ttckhl ttckp ttckhl tsu th tdov TDO (Output) tdoh |
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