LTC7803 datasheet(13/36 Pages) AD

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LTC7803

Rev 0

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OPERATION

through an external resistor. Tying FREQ to GND selects

375kHz while tying FREQ to INTVCC selects 2.25MHz.

Placing a resistor between FREQ and GND allows the fre-

quency to be programmed between 100kHz and 3MHz,

as shown in Figure 8.

Switching regulators can be particularly troublesome for

applications where electromagnetic interference (EMI) is

a concern. To improve EMI, the LTC7803 can operate in

spread spectrum mode, which is enabled by tying the

PLLIN/SPREAD pin to INTVCC. This feature varies the

switching frequency with typical boundaries of 0% to

+20% of the frequency set by the FREQ pin.

A phase-locked loop (PLL) is available on the LTC7803

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/SPREAD pin. The

LTC7803’s phase detector (PFD) and low pass filter adjust

the voltage) of the VCO input to align the turn-on of the

controller’s external top MOSFET to the rising edge of the

synchronizing signal.

The VCO input voltage is prebiased to the free running

frequency set by the FREQ pin before the external clock

is applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock to the rising edge of TG. For more rapid

lock-in to the external clock, use the FREQ pin to set the

internal oscillator to approximately the frequency of the

external clock. The LTC7803’s PLL is guaranteed to lock

to an external clock source whose frequency is between

100kHz and 3MHz.

The PLLIN/SPREAD pin is TTL compatible with thresholds

of 1.6V (rising) and 1.1V (falling) and is guaranteed to

operate with a clock signal swing of 0.5V to 2.5V.

Output Overvoltage Protection

An overvoltage comparator guards against transient

overshoots as well as other more serious conditions that

may overvoltage the output. When the VFB pin rises by

more than 10% above its regulation point of 0.8V, the top

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

Foldback Current

When the output voltage falls to less than 50% of its

nominal level, foldback current limiting is activated, pro-

gressively lowering the peak current limit in proportion to

the severity of the overcurrent or short-circuit condition.

Foldback current limiting is disabled during the soft-start

interval (as long as the VFB voltage is keeping up with the

TRACK/SS voltage).

BOOST Supply Refresh and Internal Charge Pump

The top MOSFET driver is biased from the floating boot-

strap capacitor, CB, which normally recharges during each

cycle through an external diode when the bottom MOSFET

turns on. There is an internal charge pump that keeps the

required bias on BOOST. The charge pump always oper-

ates in both forced continuous mode and pulse-skipping

mode. In Burst Mode operation, the charge pump is turned

off during sleep and enabled when the chip wakes up. The

internal charge pump can normally supply a charging cur-

rent of 65μA.

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