LTC7803 datasheet(22/36 Pages) AD

22 / 36 page

LTC7803

Rev 0

For more information www.analog.com

MOSFET. For a typical application, a value of CB = 0.1µF

is generally sufficient.

The external diode DB can be a Schottky diode or P-N

Junction diode, but in either case it should have low leak-

age and fast recovery. Pay close attention to the reverse

leakage at high temperatures, where it generally increases

substantially.

The topside MOSFET driver includes an internal charge

pump that delivers current to the bootstrap capacitor

when the top MOSFET is on continuously, such as when

the output is in dropout (100% duty cycle). The boost

diode should have a reverse leakage less than the avail-

able output current the charge pump can supply. Curves

displaying the available charge pump current under dif-

ferent operating conditions can be found in the Typical

Performance Characteristics section.

Phase-Locked Loop and Frequency Synchronization

The LTC7803 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass filter,

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET to be locked to the rising edge

of an external clock signal applied to the PLLIN/SPREAD

pin. The phase detector is an edge sensitive digital type

that provides zero degrees phase shift between the exter-

nal and internal oscillators. This type of phase detector

does not exhibit false lock to harmonics of the external

clock.

If the external clock frequency is greater than the inter-

nal oscillator’s frequency, fOSC, then current is sourced

continuously from the phase detector output, pulling up

the VCO input. When the external clock frequency is less

than fOSC, current is sunk continuously, pulling down the

VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

CLP, holds the voltage at the VCO input. Note that the

LTC7803 can only be synchronized to an external clock

whose frequency is within range of the LTC7803’s internal

VCO, which is nominally 100kHz to 3MHz.

This is guaranteed to be between 100kHz and 3MHz.

Typically, the external clock (on the PLLIN/MODE pin)

input high threshold is 1.6V, while the input low thresh-

old is 1.1V.

Rapid phase locking can be achieved by using the FREQ

pin to set a free-running frequency near the desired syn-

chronization frequency. The VCO’s input voltage is prebi-

ased at a frequency corresponding to the frequency set

by the FREQ pin. Once prebiased, the PLL only needs

to adjust the frequency slightly to achieve phase lock

and synchronization. Although it is not required that the

free-running frequency be near external clock frequency,

doing so will prevent the operating frequency from pass-

ing through a large range of frequencies as the PLL locks.

When synchronized to an external clock, the LTC7803

operates in forced continuous mode if the MODE pin is

set to Burst Mode operation or forced continuous opera-

tion. If the MODE pin is set to pulse-skipping operation,

the LTC7803 maintains pulse-skipping operation when

synchronized.

APPLICATIONS INFORMATION

LTC7803 Datasheet(PDF) 22 Page - Analog Devices

LTC7803 Datasheet(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL