LM7310 datasheet(19/44 Pages) TI

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7.3.9 Power Good Indication (PG)

The LM73100 provides an active high digital output (PG) which serves as a power good indication signal and is

asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an

open-drain pin and needs to be pulled up to an external supply.

After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on

in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush

sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time

(tPGA).

PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device

detects a fault. The PG de-assertion de-glitch time is tPGD.

Time

OUT

VPG

VHGate

VOUT + 2.8V

EN/UVLO

VUVLO(R)

Slew rate (dVdt) controlled

startup/Inrush current limiting

VIN

IINRUSH

IOUT

tPGA

VIN

dVdt

Device Enabled

PGTH

VPGTH(F)

VPGTH(R)

Figure 7-11. LM73100 PG Timing Diagram

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LM7310

SNOSDC0 – OCTOBER 2020

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