ADSP-SC570 datasheet(5/142 Pages) AD

5 / 142 page

Rev. B

Page 5 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

ARM CORTEX-A5 PROCESSOR

The ARM Cortex-A5 processor (see Figure 2) is a high perfor-

mance processor with the following features:

• Instruction cache unit (32 Kb) and data Level 1 (L1) cache

unit (32 Kb)

• In order pipeline with dynamic branch prediction

• ARM, Thumb, and ThumbEE instruction set support

•ARM TrustZone

® security extensions

• Harvard L1 memory system with a memory management

unit (MMU)

• ARM v7 debug architecture

• Trace support through an embedded trace macrocell

(ETM) interface

• Extension—vector floating-point unit (IEEE754) with trap-

less execution

• Extension—media processing engine (MPE) with NEON

technology

• Extension—Jazelle

® hardware acceleration

Figure 2. ARM Cortex-A5 Processor Block Diagram

DATA STORE

BUFFER (STB)

BUS INTERFACE UNIT (BIU)

PREFETCH UNIT AND BRANCH PREDICTOR (PFU)

DATA PROCESSING UNIT (DPU)

DATA MICRO TLB

INSTRUCTION MICRO TLB

DEBUG

DATA CACHE

UNIT (DCU)

MAIN TRANSMISSION

LOOKINSIDE BUFFER (TLB)

INSTRUCTION CACHE

UNIT (ICU)

EMBEDDED TRACE MACROCELL

(ETM) INTERFACE

L2 CACHE

CONTROLLER

(CoreLinkTM PL310)

256 Kb

SYSTEM FABRIC

TO OTHER CORES

CoreSight INTERFACE

CP15

NEON MEDIA

PROCESSING

ENGINE

32 Kb

GENERIC INTERRUPT

CONTROLLER

(PrimeCell® PL390)

DATA MASTER PORTS

SHARC PROCESSORS

ARM Cortex-A5 BUS MASTER PORT

®®

ARM Cortex-A5

PROCESSOR

®®

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