ADSP-SC570 datasheet(27/142 Pages) AD

27 / 142 page

Rev. B

Page 27 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

SPT_BD1

InOut

Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to

transmit serial data or as an input to receive serial data.

SPT_BFS

InOut

Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either

generated internally or externally.

SPT_BTDV

Output

Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in

multichannel transmit mode. It is asserted during enabled slots.

SYS_BMODE[n]

Input

Boot Mode Control n. Selects the boot mode of the processor.

SYS_CLKIN0

Input

Clock/Crystal Input.

SYS_CLKIN1

Input

Clock/Crystal Input.

SYS_CLKOUT

Output

Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter

of the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details.

SYS_FAULT

InOut

Active-High Fault Output. Indicates internal faults or senses external faults depending on the

operating mode.

SYS_FAULT

InOut

Active-Low Fault Output. Indicates internal faults or senses external faults depending on the

operating mode.

SYS_HWRST

Input

Processor Hardware Reset Control. Resets the device when asserted.

SYS_RESOUT

Output

Reset Output. Indicates the device is in the reset state.

SYS_XTAL0

Output

Crystal Output.

SYS_XTAL1

Output

Crystal Output.

TM_ACI[n]

Input

Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.

TM_ACLK[n]

Input

Alternate Clock n. Provides an additional time base for an individual timer.

TM_CLK

Input

Clock. Provides an additional global time base for all GP timers.

TM_TMR[n]

InOut

Timer n. The main input/output signal for each timer.

TRACE_CLK

Output

Trace Clock. Clock output.

TRACE_D[nn]

Output

Trace Data n. Unidirectional data bus.

TWI_SCL

InOut

Serial Clock. Clock output when master, clock input when slave.

TWI_SDA

InOut

Serial Data. Receives or transmits data.

UART_CTS

Input

Clear to Send. Flow control signal.

UART_RTS

Output

Request to Send. Flow control signal.

UART_RX

Input

Receive. Receives input. Typically connects to a transceiver that meets the electrical requirements of

the device being communicated with.

UART_TX

Output

Transmit. Transmits output. Typically connects to a transceiver that meets the electrical requirements

of the device being communicated with.

USB_CLKIN

Input

Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet

specifications for frequency/tolerance information.

USB_DM

InOut

Data –. Bidirectional differential data line.

USB_DP

InOut

Data +. Bidirectional differential data line.

USB_ID

Input

OTG ID. Senses whether the controller is a host or device. This signal is pulled low when an A type

plug is sensed (signifying that the USB controller is the A device). The input is high when a B type plug

is sensed (signifying that the USB controller is the B device).

USB_VBC

Output

VBUS Control. Controls an external voltage source to supply VBUS when in host mode. Can be

configured as open-drain. Polarity is configurable as well.

USB_VBUS

InOut

Bus Voltage. Connects to bus voltage in host and device modes.

USB_XTAL

Output

Crystal. Drives an external crystal. Must be left unconnected if an external clock is driving USB_CLKIN.

Table 11. ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions (Continued)

Signal Name

Direction

Description

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