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ADSP-SC570 Datasheet(PDF) 96 Page - Analog Devices |
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ADSP-SC570 Datasheet(HTML) 96 Page - Analog Devices |
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96 / 142 page  Rev. B | Page 96 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 66. SPI2 Port—Slave Timing1 Parameter Min Max Unit Timing Requirements tSPICHS SPIx_CLK High Period2 0.5 × tSPICLKEXT – 1.5 ns tSPICLS SPIx_CLK Low Period2 0.5 × tSPICLKEXT – 1.5 ns tSPICLK SPIx_CLK Period2 tSPICLKEXT – 1.5 ns tHDS Last SPIx_CLK Edge to SPIx_SS Not Asserted 5 ns tSPITDS Sequential Transfer Delay tSPICLKEXT – 1.5 ns tSDSCI SPIx_SS Assertion to First SPIx_CLK Edge 10.5 ns tSSPID Data Input Valid to SPIx_CLK Edge (Data Input Setup) 2 ns tHSPID SPIx_CLK Sampling Edge to Data Input Invalid 1.6 ns Switching Characteristics tDSOE SPIx_SS Assertion to Data Out Active 0 14 ns tDSDHI SPIx_SS Deassertion to Data High Impedance 0 11.5 ns tDDSPID SPIx_CLK Edge to Data Out Valid (Data Out Delay) 14 ns tHDSPID SPIx_CLK Edge to Data Out Invalid (Data Out Hold) 1.5 ns 1 All specifications apply to SPI2 only. 2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external SPIx_CLK ideal maximum frequency, see the fSPICLKTEXT specification in Table 27. Figure 37. SPI Port—Slave Timing tSPICLK tHDS tSPITDS tSDSCI tSPICLS tSPICHS tDSOE tDDSPID tDDSPID tDSDHI tHDSPID tSSPID tDSDHI tHDSPID tDSOE tHSPID tSSPID tDDSPID SPIx_SS (INPUT) SPIx_CLK (INPUT) tHSPID DATA OUTPUTS (SPIx_MISO) CPHA = 1 CPHA = 0 DATA INPUTS (SPIx_MOSI) DATA OUTPUTS (SPIx_MISO) DATA INPUTS (SPIx_MOSI) |
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