ADSP-SC570 datasheet(19/142 Pages) AD

19 / 142 page

Rev. B

Page 19 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

The USB clock is provided through a dedicated external crystal

or crystal oscillator.

The USB OTG dual-role device controller includes a phase-

locked loop (PLL) with programmable multipliers to generate

the necessary internal clocking frequency for the USB.

Media Local Bus (MediaLB)

The automotive model has a Microchip MediaLB (MLB) slave

interface that allows the processors to function as a media local

bus device. It includes support for both 3-pin and 6-pin media

local bus protocols. The MLB 3-pin configuration supports

speeds up to 1024 × FS. The MLB 6-pin configuration supports

speed of 2048 × FS. The MLB also supports up to 64 logical

channels with up to 468 bytes of data per MLB frame.

The MLB interface supports MOST25, MOST50, and MOST150

data rates and operates in slave mode only.

2-Wire Controller Interface (TWI)

The processors include three 2-wire interface (TWI) modules

that provide a simple exchange method of control data between

multiple devices. The TWI module is compatible with the

widely used I2C bus standard. The TWI module offers the

capabilities of simultaneous master and slave operation and

support for both 7-bit addressing and multimedia data arbitra-

tion. The TWI interface utilizes two pins for transferring clock

(TWI_SCL) and data (TWI_SDA) and supports the protocol at

speeds up to 400 kb/sec. The TWI interface pins are compatible

with 5 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

General-Purpose I/O (GPIO)

Each general-purpose port pin can be individually controlled by

manipulating the port control, status, and interrupt registers:

• GPIO direction control register specifies the direction of

each individual GPIO pin as input or output.

• GPIO control and status registers have a write one to mod-

ify mechanism that allows any combination of individual

GPIO pins to be modified in a single instruction, without

affecting the level of any other GPIO pins.

• GPIO interrupt mask registers allow each individual GPIO

pin to function as an interrupt to the processors. GPIO pins

defined as inputs can be configured to generate hardware

interrupts, while output pins can be triggered by software

interrupts.

• GPIO interrupt sensitivity registers specify whether indi-

vidual pins are level or edge sensitive and specify, if edge

sensitive, whether the rising edge or both the rising and

falling edges of the signal are significant.

Pin Interrupts

Every port pin on the processors can request interrupts in either

an edge sensitive or a level sensitive manner with programmable

polarity. Interrupt functionality is decoupled from GPIO opera-

tion. Five system level interrupt channels (PINT0–PINT4) are

reserved for this purpose. Each of these interrupt channels can

manage up to 32 interrupt pins. The assignment from pin to

interrupt is not performed on a pin by pin basis. Rather, groups

of eight pins (half ports) can be flexibly assigned to interrupt

channels.

Every pin interrupt channel features a special set of 32-bit mem-

ory-mapped registers that enable half-port assignment and

interrupt management. This includes masking, identification,

and clearing of requests. These registers also enable access to the

respective pin states and use of the interrupt latches, regardless

of whether the interrupt is masked or not. Most control registers

feature multiple MMR address entries to write one to set or

write one to clear them individually.

Mobile Storage Interface (MSI)

The mobile storage interface (MSI) controller acts as the host

interface for multimedia cards (MMC), secure digital memory

cards (SD), and secure digital input/output cards (SDIO). The

MSI controller has the following features:

• Support for a single MMC, SD memory, and SDIO card

• Support for 1-bit and 4-bit SD modes

• Support for 1-bit, 4-bit, and 8-bit MMC modes

• Support for eMMC 4.3 embedded NAND flash devices

• An 11-signal external interface with clock, command,

optional interrupt, and up to eight data lines

• Integrated DMA controller

• Card interface clock generation in the clock distribution

unit (CDU)

• SDIO interrupt and read wait features

SYSTEM ACCELERATION

The following sections describe the system acceleration blocks

of the ADSP-SC57x/ADSP-2157x processors.

Finite Impulse Response (FIR) Accelerator

The finite impulse response (FIR) accelerator consists of a

1024 word coefficient memory, a 1024 word deep delay line for

the data, and four MAC units. A controller manages the acceler-

ator. The FIR accelerator runs at the peripheral clock frequency.

The FIR accelerator can access all memory spaces and can run

concurrently with the other accelerators on the processor.

Infinite Impulse Response (IIR) Accelerator

The infinite impulse response (IIR) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data, and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency. The IIR

accelerator can access all memory spaces and run concurrently

with the other accelerators on the processor.

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