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ADSP-SC570 Datasheet(PDF) 60 Page - Analog Devices |
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ADSP-SC570 Datasheet(HTML) 60 Page - Analog Devices |
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60 / 142 page ![]() Rev. B | Page 60 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ELECTRICAL CHARACTERISTICS Parameter Conditions Min Typ Max Unit VOH 1 High Level Output Voltage At VDD_EXT = minimum, IOH = –1.0 mA 2 2.4 V VOL 1 Low Level Output Voltage At VDD_EXT = minimum, IOL = 1.0 mA 2 0.4 V VOH_DDR2 3 High Level Output Voltage for DDR2 DS = 40 Ω At VDD_DDR = minimum, IOH = –5.8 mA 1.38 V VOL_DDR2 3 Low Level Output Voltage for DDR2 DS = 40 Ω At VDD_DDR = minimum, IOL = 5.8 mA 0.32 V VOH_DDR2 3 High Level Output Voltage for DDR2 DS = 60 Ω At VDD_DDR = minimum, IOH = –3.4 mA 1.38 V VOL_DDR2 3 Low Level Output Voltage for DDR2 DS = 60 Ω At VDD_DDR = minimum, IOL = 3.4 mA 0.32 V VOH_DDR3 4 High Level Output Voltage for DDR3 DS = 40 Ω At VDD_DDR = minimum, IOH = –5.8 mA 1.105 V VOL_DDR3 4 Low Level Output Voltage for DDR3 DS = 40 Ω At VDD_DDR = minimum, IOL = 5.8 mA 0.32 V VOH_DDR3 4 High Level Output Voltage for DDR3 DS = 60 Ω At VDD_DDR = minimum, IOH = –3.4 mA 1.105 V VOL_DDR3 4 Low Level Output Voltage for DDR3 DS = 60 Ω At VDD_DDR = minimum, IOL = 3.4 mA 0.32 V VOH_LPDDR 5 High Level Output Voltage for LPDDR At VDD_DDR = minimum, IOH = –6.0 mA 1.38 V VOL_LPDDR 5 Low Level Output Voltage for LPDDR At VDD_DDR = minimum, IOL = 6.0 mA 0.32 V IIH 6, 7 High Level Input Current At VDD_EXT = maximum, VIN = VDD_EXT maximum 10 μA IIL 6 Low Level Input Current At VDD_EXT = maximum, VIN = 0 V 10 μA IIL_PU 7 Low Level Input Current Pull-Up At VDD_EXT = maximum, VIN = 0 V 200 μA IIH_PD 8 High Level Input Current Pull-Down At VDD_EXT = maximum, VIN = VDD_EXT maximum 200 μA IOZH 9 Three-State Leakage Current At VDD_EXT/VDD_DDR = maximum, VIN = VDD_EXT/VDD_DDR maximum 10 μA IOZL 9 Three-State Leakage Current At VDD_EXT/VDD_DDR = maximum, VIN = 0 V 10 μA CIN 10 Input Capacitance TCASE = 25°C 5 pF IDD_IDLE VDD_INT Current in Idle fCCLK =450 MHz ASFSHARC1 =0.32 ASFSHARC2 =0.32 ASFA5 =0.25 fSYSCLK =225 MHz fSCLK0/1 = 112.5 MHz (Other clocks are disabled) No Peripheral or DMA activity TJ = 25°C VDD_INT = 1.1 V 410 mA |
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