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ADSP-SC570 Datasheet(PDF) 97 Page - Analog Devices |
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ADSP-SC570 Datasheet(HTML) 97 Page - Analog Devices |
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97 / 142 page  Rev. B | Page 97 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SPI Port—SPIx_RDY Slave Timing SPIx_RDY provides flow control. CPOL, CPHA, and FCCH are configuration bits in the SPIx_CTL register. Table 67. SPI Port—SPIx_RDY Slave Timing1 1 All specifications apply to all three SPIs. Parameter Conditions Min Max Unit Switching Characteristic tDSPISCKRDYS SPIx_RDY Deassertion from Last Valid Input SPIx_CLK Edge FCCH = 0 3 × tSCLK1 4 × tSCLK1 + 10 ns FCCH = 1 4 × tSCLK1 5 × tSCLK1 + 10 ns Figure 38. SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) tDSPISCKRDYS SPIx_RDY (O) SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) CPHA = 1 CPHA = 0 |
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