ADSP-SC570 datasheet(14/142 Pages) AD

14 / 142 page

Rev. B

Page 14 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

Support for the hardware accelerated hash functions includes

the following:

•SHA-1

• SHA-2 with 224-bit and 256-bit digests

• HMAC transforms for SHA-1 and SHA-2

•MD5

Public key accelerator (PKA) is available to offload computation

intensive public key cryptography operations.

Both a hardware-based nondeterministic random number gen-

erator and pseudorandom number generator are available.

Secure boot is also available with 224-bit elliptic curve digital

signatures ensuring integrity and authenticity of the boot

stream. Optionally, ensuring confidentiality through AES-128

encryption is available.

Employ secure debug to allow only trusted users to access the

system with debug tools.

System Protection Unit (SPU)

The system protection unit (SPU) guards against accidental or

unwanted access to an MMR space of the peripheral by provid-

ing a write protection mechanism. The user can choose and

configure the protected peripherals as well as configure which of

the four system MMR masters (two SHARC+ cores, memory

DMA, and CoreSight debug) the peripherals are guarded

against.

The SPU is also part of the security infrastructure. Along with

providing write protection functionality, the SPU is employed

to define which resources in the system are secure or nonsecure

as well as block access to secure resources from nonsecure

masters.

System Memory Protection Unit (SMPU)

The system memory protection unit (SMPU) provides memory

protection against read and/or write transactions to defined

regions of memory. There are SMPU units in the ADSP-

SC57x/ADSP-2157x processors for each memory space, except

for SHARC L1 and SPI direct memory slave.

The SMPU is also part of the security infrastructure. It allows

the user to protect against arbitrary read and/or write transac-

tions and allows regions of memory to be defined as secure and

prevent nonsecure masters from accessing those memory

regions.

SECURITY FEATURES DISCLAIMER

To our knowledge, the Security Features, when used in accor-

dance with the data sheet and hardware reference manual

specifications, provide a secure method of implementing code

and data safeguards. However, Analog Devices does not guaran-

tee that this technology provides absolute security.

ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS

ANY AND ALL EXPRESS AND IMPLIED WARRANTIES

THAT THE SECURITY FEATURES CANNOT BE

BREACHED, COMPROMISED, OR OTHERWISE

CIRCUMVENTED AND IN NO EVENT SHALL ANALOG

DEVICES BE LIABLE FOR ANY LOSS, DAMAGE,

DESTRUCTION, OR RELEASE OF DATA, INFORMATION,

PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY.

SAFETY FEATURES

The ADSP-SC57x/ADSP-2157x processors are designed to sup-

port functional safety applications. While the level of safety is

mainly dominated by the system concept, the following primi-

tives are provided by the processors to build a robust safety

concept.

Multiparity Bit Protected SHARC+ Core L1 Memories

In the SHARC+ core L1 memory space, whether SRAM or

cache, multiple parity bits protect each word to detect the single

event upsets that occur in all RAMs. Parity also protects the

cache tags and BTB.

Parity Protected ARM L1 Cache

In the ARM Cortex-A5 L1 cache space, each word is protected

by multiple parity bits to detect the single event upsets that

occur in all RAMs. Parity also protects the cache tags.

Error Correcting Codes (ECC) Protected L2 Memories

Error correcting codes (ECC) correct single event upsets. A sin-

gle error correct/double error detect (SEC/DED) code protects

the L2 memory. By default, ECC is enabled, but it can be dis-

abled on a per bank basis. Single-bit errors correct

transparently. If enabled, dual-bit errors can issue a system

event or fault. ECC protection is fully transparent to the user,

even if L2 memory is read or written by 8-bit or 16-bit entities.

Parity-Protected Peripheral Memories

Parity protection is added to all peripheral memories:

•ASRC

• IIR

•FIR

•USB

•CAN

• CRYPTO

•EMAC

•SDIO

•MLB

•TRACE

CAUTION

This product includes security features that can be

used to protect embedded nonvolatile memory

contents and prevent execution of unauthorized

code. When security is enabled on this device

(either by the ordering party or the subsequent

receiving parties), the ability of Analog Devices to

conduct failure analysis on returned devices is

limited. Contact Analog Devices for details on the

failure analysis limitations for this device.

ADSP-SC570 Datasheet(PDF) 14 Page - Analog Devices

ADSP-SC570 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL