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ADSP-SC570 Datasheet(PDF) 58 Page - Analog Devices |
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ADSP-SC570 Datasheet(HTML) 58 Page - Analog Devices |
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58 / 142 page  Rev. B | Page 58 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Clock Related Operating Conditions Table 27 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the table applies to all speed grades except where expressly noted. Table 27. Clock Operating Conditions Parameter Restriction Min Typ Max Unit fCCLK Core Clock Frequency fCCLK ≥ fSYSCLK 100 500 MHz fSYSCLK SYSCLK Frequency1 1 When using MLB, there is a requirement that the fSYSCLK value must be a minimum of 100 MHz for both 3-pin and 6-pin modes and for all supported speeds. 250 MHz fSCLK0 SCLK0 Frequency2 2 The minimum frequency for SCLK0 applies only when using the USB. fSYSCLK ≥ fSCLK0 30 125 MHz fSCLK1 SCLK1 Frequency fSYSCLK ≥ fSCLK1 125 MHz fDCLK LPDDR Clock Frequency 200 MHz fDCLK DDR2 Clock Frequency 400 MHz fDCLK DDR3 Clock Frequency 450 MHz fOCLK Output Clock Frequency3 3 fOCLK must not exceed fSCLK0 when selected as SYS_CLKOUT. 250 MHz fSYS_CLKOUTJ SYS_CLKOUT Period Jitter 4, 5 4 SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due to the dependency on these factors, the measured jitter can be higher or lower than this typical specification for each end application. 5 The value in the Typ field is the percentage of the SYS_CLKOUT period. ±1 % fPCLKPROG Programmed PPI Clock When Transmitting Data and Frame Sync 62.5 MHz fPCLKPROG Programmed PPI Clock When Receiving Data or Frame Sync 50 MHz fPCLKEXT External PPI Clock When Receiving Data and Frame Sync6, 7 6 The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications section for that peripheral. 7 The peripheral external clock frequency must also be less than or equal to the fSCLK (fSCLK0 or fSCLK1) that clocks the peripheral. fPCLKEXT ≤ fSCLK0 62.5 MHz fPCLKEXT External PPI Clock Transmitting Data or Frame Sync6, 7 fPCLKEXT ≤ fSCLK0 50 MHz fLCLKTPROG Programmed Link Port Transmit Clock 125 MHz fLCLKREXT External Link Port Receive Clock6, 7 fLCLKEXT ≤ fSCLK0 125 MHz fSPTCLKPROG Programmed SPT Clock When Transmitting Data and Frame Sync 62.5 MHz fSPTCLKPROG Programmed SPT Clock When Receiving Data or Frame Sync 31.25 MHz fSPTCLKEXT External SPT Clock When Receiving Data and Frame Sync6, 7 fSPTCLKEXT ≤ fSCLK0 62.5 MHz fSPTCLKEXT External SPT Clock Transmitting Data or Frame Sync6, 7 fSPTCLKEXT ≤ fSCLK0 31.25 MHz fSPICLKPROG Programmed SPI2 Clock When Transmitting Data 75 MHz Programmed SPI0, SPI1 Clock When Transmitting Data 62.5 MHz fSPICLKPROG Programmed SPI2 Clock When Receiving Data 75 MHz Programmed SPI0, SPI1 Clock When Receiving Data 62.5 MHz fSPICLKEXT External SPI2 Clock When Receiving Data6, 7 fSPICLKEXT ≤ fSCLK1 75 MHz External SPI0, SPI1 Clock When Receiving Data6, 7 fSPICLKEXT ≤ fSCLK0 62.5 MHz fSPICLKEXT External SPI2 Clock When Transmitting Data6, 7 fSPICLKEXT ≤ fSCLK1 45 MHz External SPI0, SPI1 Clock When Transmitting Data6,7 fSPICLKEXT ≤ fSCLK0 62.5 MHz fACLKPROG Programmed ACM Clock 56.25 MHz |
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