LTC3129 datasheet(12/34 Pages) AD

12 / 34 page

LTC3114-1

Rev. D

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OPERATION

LEDs, charging batteries, a wide compliance range cur-

rent source or just providing a well controlled current

limit, the LTC3114-1 programmable average output

current capability delivers high efficiency and maximum

flexibility. The output current limit level is independent of

operating mode, (buck or boost), and is active down to

approximately 2V on VOUT. Below 2V on VOUT, a secondary

foldback current limit circuit is activated to reduce power

dissipation. The desired average output current level is

programmed with a standard low wattage resistor from

PROG to ground. A low loss current sense resistor and

accurate current sense amplifier are integrated within the

IC, greatly simplifying the PCB layout and design. Factory

trimming of the output current limit offset and gain pro-

vide a high degree of accuracy, typically within ±5% of

the setpoint. The applications section provides details on

how to select the programming resistor, RPROG, for the

desired average output current level from the LTC3114-1.

PWM Mode Operation

If the MODE pin is high or if the load current on the con-

verter is high enough to command PWM mode opera-

tion with MODE low, the LTC3114-1 operates in a fixed

1.2MHz PWM mode using a current mode control loop.

PWM mode minimizes output voltage ripple and yields

a low noise switching frequency spectrum. A propri-

etary switching algorithm provides seamless transitions

between operating modes and eliminates discontinuities

in the average inductor current, inductor ripple current

and loop transfer function throughout all modes of oper-

ation. These advantages result in increased efficiency,

PLDO

BST1

CBST1

CBST2

BST2

PVIN

PVOUT

SW1

SW2

PLDO

LTC3114-1

PGND

31141 F01

Figure 1. Power Stage Schematic

improved loop stability and lower output voltage ripple

in comparison to the traditional buck-boost converter.

Figure 1 shows the topology of the LTC3114-1 power stage

which is comprised of four N-channel DMOS switches and

their associated gate drivers. In PWM mode operation

both switch pins transition on every cycle independent of

the input and output voltages. In response to the internal

control loop command, an internal pulse width modulator

generates the appropriate switch duty cycle to maintain

regulation of the output voltage.

When stepping down from a high input voltage to a lower

output voltage, the converter operates in buck mode and

switch D remains on for the entire switching cycle except

for the minimum switch low duration (typically 50ns).

During the switch low duration, switch C is turned on

which forces SW2 low and charges the flying capacitor,

CBST2. This ensures that the switch D gate driver power

supply rail on BST2 is maintained. The duty cycle of

switches A and B are adjusted by the PWM to maintain

output voltage regulation in buck mode.

If the input voltage is lower than the output voltage, the

converter operates in boost mode. Switch A remains on

for the entire switching cycle except for the minimum

switch low duration (typically 100ns). During the switch

low duration, switch B is turned on which forces SW1

low and charges the flying capacitor, CBST1. This ensures

that the switch A gate driver power supply rail on BST1

is maintained. The duty cycle of switches C and D are

adjusted by the PWM to maintain output voltage regula-

tion in boost mode.

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