LTC3129 datasheet(16/34 Pages) AD

16 / 34 page

LTC3114-1

Rev. D

For more information www.analog.com

OPERATION

slightly above zero current to compensate for comparator

propagation delay. In some cases, the inductor current

may reverse slightly if there is a very high voltage output

or small inductor resulting in a small amount of resid-

ual energy left in the inductor following a zero current

event. In this case the LTC3114-1 SW1 waveform will

display a characteristic half sine wave between the time

at which Izero is detected and when the next switching

cycle commences. This is because SWC is the only active

(on) switch following an IZERO event and this behavior is

not harmful to the LTC3114-1.

Burst Mode Operation

When the MODE pin is held low, the LTC3114-1 is config-

ured for Burst Mode operation. As a result, the buck-boost

DC/DC converter will operate with normal continuous

PWM switching above a predetermined minimum out-

put load and will automatically transition to power saving

Burst Mode operation below this output load level. Refer

to the Typical Performance Characteristics section of this

data sheet to determine the Burst Mode transition thresh-

old for various combinations of VIN and VOUT. If MODE

is low, at light output loads, the LTC3114-1 will go into a

standby or sleep state when the output voltage achieves

its nominal regulation level. The sleep state halts PWM

switching and powers down all non-essential functions

of the IC, significantly reducing the quiescent current of

the LTC3114-1. This greatly improves overall power con-

version efficiency when the output load is light. Since the

converter is not operating in sleep, the output voltage will

slowly decay at a rate determined by the output load resis-

tance and the output capacitor value. When the output

voltage has decayed by a small amount, typically 1%, the

LTC3114-1 will wake and resume normal PWM switch-

ing operation until the voltage on VOUT is restored to the

previous level. If the load is very light, the LTC3114-1

may only need to switch for a few cycles to restore VOUT

and may sleep for extended periods of time, significantly

improving efficiency.

Soft-Start

The LTC3114-1 soft-start circuit minimizes input current

transients and output voltage overshoot on initial power

up. The required timing components for soft-start are

internal to the LTC3114-1 and produce a nominal soft-

start duration of approximately 2ms. The internal soft-

start circuit slowly ramps the error amplifier output, VC.

In doing so, the current command of the IC is also slowly

increased, starting from zero. It is unaffected by output

loading or output capacitor value. Soft-start is reset by

undervoltage lockout on both VIN and LDO, the accurate

RUN pin comparator, thermal shutdown and the overload

current limit as described previously.

LDO REGULATOR

An internal low dropout regulator generates a nominal

4.4V rail from VIN. The LDO rail powers the internal control

circuitry and power device gate drivers of the LTC3114-1.

The LDO regulator is disabled in shutdown to reduce qui-

escent current and is enabled by forcing the RUN pin

above its logic threshold. The LDO regulator includes

current-limit protection to safeguard against accidental

short-circuiting of the LDO rail. In 5V VOUT applications,

the LDO can be driven by VOUT through a Schottky diode,

commonly referred to as bootstrapping. Bootstrapping

can provide a significant efficiency improvement, partic-

ularly when VIN is very high and also allows operation to

the minimum rated input voltage of 2.2V.

UNDERVOLTAGE LOCKOUT

The LTC3114-1 undervoltage lockout (UVLO) circuit dis-

ables operation of the internal power switches and keeps

other IC functions in a reset state if either the input voltage

applied to VIN or the LDO output voltage are below their

respective UVLO thresholds. There are two UVLO circuits,

one that monitors VIN and another that monitors LDO. The

VIN UVLO comparator has a falling voltage threshold of

2.1V (typical). If VIN falls below this level, IC operation is

disabled until VIN rises above 2.2V (typical), as long as

the LDO voltage is above its UVLO threshold. The LDO

UVLO has a falling voltage threshold of 2.4V (typical). If

the LDO voltage falls below this threshold, IC operation

is disabled until LDO rises above 2.5V (typical) as long as

VIN is above its nominal UVLO threshold level.

LTC3129 Datasheet(PDF) 16 Page - Analog Devices

LTC3129 Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL