RX113 datasheet(80/131 Pages) RENESAS

80 / 131 page

R01DS0216EJ0120 Rev.1.20

Page 80 of 131

Sep 07, 2020

RX113 Group

5. Electrical Characteristics

5.3.2

Reset Timing

Note 1. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b.

Note 2. When OFS1.(STUPLVD1REN, FASTSTUP)

≠ 11b.

Note 3. When IWDTCR.CKS[3:0] = 0000b.

Figure 5.26

Reset Input Timing at Power-On

Figure 5.27

Reset Input Timing (1)

Figure 5.28

Reset Input Timing (2)

Table 5.23

Reset Timing

Conditions: 1.8 V

≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, T

a = –40 to +105°C

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

RES# pulse width

At power-on

tRESWP

—

Figure 5.26

Other than above

tRESW

—

µs

Figure 5.27

Wait time after RES#

cancellation

(at power-on)

At normal startup*1

tRESWT

—

8.5

—

Figure 5.26

During fast startup time*2

tRESWT

—

560

—

µs

Wait time after RES# cancellation

(during powered-on state)

tRESWT

—

114

—

µs

Figure 5.27

Independent watchdog timer reset period

tRESWIW

—1

—

IWDT clock

cycle

Figure 5.28

Software reset period

tRESWSW

—

ICLK cycle

Wait time after independent watchdog timer reset cancellation*3

tRESW2

—

300

—

µs

Wait time after software reset cancellation

tRESW2

—

168

—

µs

VCC

RES#

tRESWP

Internal reset

tRESWT

RES#

Internal reset

tRESWT

tRESW

Independent watchdog timer reset

Software reset

Internal reset

tRESWT2

tRESWIW, tRESWSW

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