RX113 datasheet(86/131 Pages) RENESAS

86 / 131 page

R01DS0216EJ0120 Rev.1.20

Page 86 of 131

Sep 07, 2020

RX113 Group

5. Electrical Characteristics

Note 1. tPcyc: PCLK cycle

Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)

Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)

Table 5.31

Timing of On-Chip Peripheral Modules (2)

Conditions: 1.8 V

≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,

Ta = –40 to +105°C, C = 30 pF

Item

Symbol

Min.

Max.

Unit

Test

Conditions

RSPI

RSPCK clock cycle

Master

tSPcyc

4096

tPcyc*1 Figure 5.42

Slave

8—

RSPCK clock

high pulse width

Master

tSPCKWH (tSPcyc – tSPCKr –

tSPCKf)/2 – 3

—ns

Slave

(tSPcyc – tSPCKr –

tSPCKf)/2

—

RSPCK clock

low pulse width

Master

tSPCKWL

(tSPcyc – tSPCKr –

tSPCKf)/2 – 3

—ns

Slave

(tSPcyc – tSPCKr –

tSPCKf)/2

—

RSPCK clock

rise/fall time

Output

2.7 V or above

tSPCKr,

tSPCKf

—10

1.8 V or above

—15

Input

—1

µs

Data input setup time

Master

2.7 V or above

tSU

—

Figure 5.43

Figure 5.48

1.8 V or above

—

Slave

25 – tPcyc

—

Data input hold time

Master

RSPCK set to a division

ratio other than PCLKB

divided by 2

tPcyc

—ns

RSPCK set to PCLKB

divided by 2

tHF

0—

Slave

20 + 2 × tPcyc

—

SSL setup time

Master

tLEAD

–30 + N*2 ×

tSPcyc

—ns

Slave

2—

tPcyc

SSL hold time

Master

tLAG

–30 + N*3 ×

tSPcyc

—ns

Slave

2—

tPcyc

Data output delay time

Master

2.7 V or above

tOD

—14

1.8 V or above

—30

Slave

2.7 V or above

—3 × tPcyc + 65

1.8 V or above

—3 × tPcyc + 105

Data output hold time

Master

2.7 V or above

tOH

0—

1.8 V or above

–20

—

Slave

0—

Successive

transmission delay

time

Master

tTD

tSPcyc + 2 × tPcyc

8 × tSPcyc + 2 ×

tPcyc

Slave

4 × tPcyc

—

MOSI and MISO rise/

fall time

Output

2.7 V or above

tDr, tDf

—10

1.8 V or above

—20

Input

—1

µs

SSL rise/fall time

Output

tSSLr,

tSSLf

—20

Input

—1

µs

Slave access time

2.7 V or above

tSA

—6

tPcyc

Figure 5.47,

Figure 5.48

1.8 V or above

—7

Slave output release time

2.7 V or above

tREL

—5

tPcyc

1.8 V or above

—6

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