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RX113 Datasheet(PDF) 88 Page - Renesas Technology Corp |
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RX113 Datasheet(HTML) 88 Page - Renesas Technology Corp |
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88 / 131 page  R01DS0216EJ0120 Rev.1.20 Page 88 of 131 Sep 07, 2020 RX113 Group 5. Electrical Characteristics Note: tIICcyc: RIIC internal reference count clock (IICφ) cycle Note 1. The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE bit = 1. Note 2. The minimum tsr and tsf specifications for fast mode are not set. Table 5.33 Timing of On-Chip Peripheral Modules (4) Conditions: 2.7 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz, Ta = –40 to +105°C Item Symbol Min.*1 Max. Unit Test Conditions RIIC (Standard mode, SMBus) SCL0 input cycle time tSCL 6 (12) × tIICcyc + 1300 — ns Figure 5.49 SCL0 input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns SCL0 input low pulse width tSCLL 3 (6) × tIICcyc + 300 — ns SCL0, SDA0 input rise time tSr — 1000 ns SCL0, SDA0 input fall time tSf — 300 ns SCL0, SDA0 input spike pulse removal time tSP 01 (4) × tIICcyc ns SDA0 input bus free time tBUF 3 (6) × tIICcyc + 300 — ns START condition input hold time tSTAH tIICcyc + 300 — ns Repeated START condition input setup time tSTAS 1000 — ns STOP condition input setup time tSTOS 1000 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0— ns SCL0, SDA0 capacitive load Cb — 400 pF RIIC (Fast mode) SCL0 input cycle time tSCL 6 (12) × tIICcyc + 600 — ns Figure 5.49 SCL0 input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns SCL0 input low pulse width tSCLL 3 (6) × tIICcyc + 300 — ns SCL0, SDA0 input rise time tSr —*2 300 ns SCL0, SDA0 input fall time tSf —*2 300 ns SCL0, SDA0 input spike pulse removal time tSP 01 (4) × tIICcyc ns SDA0 input bus free time tBUF 3 (6) × tIICcyc + 300 — ns START condition input hold time tSTAH tIICcyc + 300 — ns Repeated START condition input setup time tSTAS 300 — ns STOP condition input setup time tSTOS 300 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0— ns SCL0, SDA0 capacitive load Cb — 400 pF |
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