 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AT90PWM2 Datasheet(PDF) 130 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT90PWM2 Datasheet(HTML) 130 Page - ATMEL Corporation |
|
|
130 / 365 page  130 AT90PWM2/3 4317B–AVR–02/05 Timer/Counter1 Interrupt Mask Register – TIMSK1 • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM2/3, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo- bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “Reset and Interrupt Vectors Placement in AT90PWM2/3(1)” on page 57) is executed when the ICF1 Flag, located in TIFR1, is set. • Bit 4, 3 – Res: Reserved Bits These bits are unused bits in the AT90PWM2/3, and will always read as zero. • Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo- bally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see “Reset and Interrupt Vectors Placement in AT90PWM2/3(1)” on page 57) is executed when the OCF1B Flag, located in TIFR1, is set. • Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo- bally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Reset and Interrupt Vectors Placement in AT90PWM2/3(1)” on page 57) is executed when the OCF1A Flag, located in TIFR1, is set. • Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo- bally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (see “Reset and Interrupt Vectors Placement in AT90PWM2/3(1)” on page 57) is executed when the TOV1 Flag, located in TIFR1, is set. Timer/Counter1 Interrupt Flag Register – TIFR1 • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM2/3, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alter- natively, ICF1 can be cleared by writing a logic one to its bit location. • Bit 4, 3 – Res: Reserved Bits Bit 765 43 2 1 0 – – ICIE1 – – OCIE1B OCIE1A TOIE1 TIMSK1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 432 10 –– ICF1 –– OCF1B OCF1A TOV1 TIFR1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
