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AT90PWM2 Datasheet(PDF) 171 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 171 Page - ATMEL Corporation |
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171 / 365 page  171 AT90PWM2/3 4317A-3–AVR–02/05 PSC 0 Configuration Register – PCNF0 PSC 1 Configuration Register – PCNF1 PSC 2 Configuration Register – PCNF2 The PSC n Configuration Register is used to configure the running mode of the PSC. • Bit 7 - PFIFTYn: PSC n Fifty Writing this bit to one, set the PSC in a fifty percent mode where only OCRnRBH/L and OCRnSBH/L are used. They are duplicated in OCRnRAH/L and OCRnSAH/L during the update of OCRnRBH/L. This feature is useful to perform fifty percent waveforms. • Bit 6 - PALOCKn: PSC n Autolock When this bit is set, the Output Compare Registers RA, SA and SB can be written with- out disturbing the PSC cycles. The update of the PSC internal registers will be done at the end of the PSC cycle if the Output Compare Register RB has been the last written. When set, this bit prevails over LOCK (bit 5) • Bit 5 – PLOCKn: PSC n Lock When this bit is set, the Output Compare Registers RA, RB, SA and SB can be written without disturbing the PSC cycles. The update of the PSC internal registers will be done if the LOCK bit is released to zero. • Bit 4:3 – PMODEn1: 0: PSC n Mode Select the mode of PSC. • Bit 2 – POPn: PSC n Output Polarity If this bit is cleared, the PSC outputs are active Low. If this bit is set, the PSC outputs are active High. Bit 7 65 43 21 0 PFIFTY0 PALOCK0 PLOCK0 PMODE01 PMODE00 POP0 PCLKSEL0 - PCNF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 21 0 PFIFTY1 PALOCK1 PLOCK1 PMODE11 PMODE10 POP1 PCLKSEL1 - PCNF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 21 0 PFIFTY2 PALOCK2 PLOCK2 PMODE21 PMODE20 POP2 PCLKSEL2 POME2 PCNF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 64. PSC n Mode Selection PMODEn1 PMODEn0 Description 0 0 One Ramp Mode 0 1 Two Ramp Mode 1 0 Four Ramp Mode 1 1 Center Aligned Mode |
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