AT90PWM2 datasheet(174/365 Pages) ATMEL

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174

AT90PWM2/3

4317A-3–AVR–02/05

PSC 1 Control Register –

PCTL1

• Bit 7:6 – PPRE11:0 : PSC 1 Prescaler Select

This two bits select the PSC input clock division factor.All generated waveform will be

modified by this factor.

• Bit 5 – PBFM1 : Balance Flank Width Modulation

When this bit is clear, Flank Width Modulation operates on On-Time 1 only.

When this bit is set, Flank Width Modulation operates on On-Time 0 and On-Time 1.

• Bit 4 – PAOC1B : PSC 1 Asynchronous Output Control B

When this bit is set, Fault input selected to block B can act directly to PSCOUT11 out-

put. See Section “PSC Clock Sources”, page 165

• Bit 3 – PAOC1A : PSC 1 Asynchronous Output Control A

When this bit is set, Fault input selected to block A can act directly to PSCOUT10 out-

put. See Section “PSC Clock Sources”, page 165

• Bit 2 – PARUN1 : PSC 1 Autorun

When this bit is set, the PSC 1 starts with PSC0. That means that PSC 1 starts :

•

when PRUN0 bit in PCTL0 register is set,

•

or when PARUN0 bit in PCTL0 is set and PRUN2 bit in PCTL2 register is set.

Thanks to this bit, 2 or 3 PSCs can be synchronized (motor control for example)

• Bit 1 – PCCYC1 : PSC 1 Complete Cycle

When this bit is set, the PSC 1 completes the entire waveform cycle before halt opera-

tion requested by clearing PRUN1. This bit is not relevant in slave mode (PARUN1 = 1).

• Bit 0 – PRUN1 : PSC 1 Run

Writing this bit to one starts the PSC 1.

When set, this bit prevails over PARUN1 bit.

Bit

PPRE11

PPRE10

PBFM1

PAOC1B

PAOC1A

PARUN1

PCCYC1

PRUN1

PCTL1

Read/Write

R/W

Initial Value

Table 66. PSC 1 Prescaler Selection

PPRE11

PPRE10

Description

No divider on PSC input clock

Divide the PSC input clock by 4

Divide the PSC input clock by 16

Divide the PSC clock by 64

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