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AT90PWM2 Datasheet(PDF) 178 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 178 Page - ATMEL Corporation |
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178 / 365 page  178 AT90PWM2/3 4317A-3–AVR–02/05 PSC 0 Input Capture Register – PICR0H and PICR0L PSC 1 Input Capture Register – PICR1H and PICR1L PSC 2 Input Capture Register – PICR2H and PICR2L The Input Capture is updated with the PSC counter value each time an event occurs on the enabled PSC input pin (or optionally on the Analog Comparator output) if the capture function is enabled (bit PCAEnx in PFRCnx register is set). The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is per- formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit or 12-bit registers. This register is read only and a write operation to this register is not allowed. PSC2 Specific Register PSC 2 Output Matrix – POM2 • Bit 7 – POMV2B3: Output Matrix Output B Ramp 3 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 3 • Bit 6 – POMV2B2: Output Matrix Output B Ramp 2 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 2 • Bit 5 – POMV2B1: Output Matrix Output B Ramp 1 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 1 • Bit 4 – POMV2B0: Output Matrix Output B Ramp 0 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 0 Bit 765 432 10 – – – – PICR0[11:8] PICR0H PICR0[7:0] PICR0L Read/Write RR RRR RRR Initial Value 000 000 00 Bit 765 432 10 – – – – PICR1[11:8] PICR1H PICR1[7:0] PICR1L Read/Write RR RRR RRR Initial Value 000 000 00 Bit 765 432 10 – – – – PICR2[11:8] PICR2H PICR2[7:0] PICR2L Read/Write RR RRR RRR Initial Value 000 000 00 Bit 7 65 43 21 0 POMV2B3 POMV2B2 POMV2B1 POMV2B0 POMV2A3 POMV2A2 POMV2A1 POMV2A0 POM2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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