AT90PWM2 datasheet(182/365 Pages) ATMEL

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182

AT90PWM2/3

4317B–AVR–02/05

Serial Peripheral Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between the AT90PWM2/3 and peripheral devices or between several AVR devices.

The AT90PWM2/3 SPI includes the following features:

Features

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

Figure 94. SPI Block Diagram(1)

Note:

1. Refer to Figure 1 on page 3, and Table 24 on page 70 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 95.

The system consists of two shift Registers, and a Master clock generator. The SPI Mas-

ter initiates the communication cycle when pulling low the Slave Select SS pin of the

desired Slave. Master and Slave prepare the data to be sent in their respective shift

Registers, and the Master generates the required clock pulses on the SCK line to inter-

DIVIDER

/2/4/8/16/32/64/128

clk

MISO

MOSI

SCK

SS_A

SPIPS

AT90PWM2 Datasheet(PDF) 182 Page - ATMEL Corporation