AT90PWM2 datasheet(179/365 Pages) ATMEL

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179

AT90PWM2/3

4317A-3–AVR–02/05

• Bit 3 – POMV2A3: Output Matrix Output A Ramp 3

This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 3

• Bit 2 – POMV2A2: Output Matrix Output A Ramp 2

This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 2

• Bit 1 – POMV2A1: Output Matrix Output A Ramp 1

This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 1

• Bit 0 – POMV2A0: Output Matrix Output A Ramp 0

This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 0

PSC0 Interrupt Mask Register

– PIM0

PSC1 Interrupt Mask Register

– PIM1

PSC2 Interrupt Mask Register

– PIM2

• Bit 5 – PSEIEn : PSC n Synchro Error Interrupt Enable

When this bit is set, the PSEIn bit (if set) generate an interrupt.

• Bit 4 – PEVEnB : PSC n External Event B Interrupt Enable

When this bit is set, an external event which can generates a capture from Retrig-

ger/Fault block B generates also an interrupt.

• Bit 3 – PEVEnA : PSC n External Event A Interrupt Enable

When this bit is set, an external event which can generates a capture from Retrig-

ger/Fault block A generates also an interrupt.

• Bit 0 – PEOPEn : PSC n End Of Cycle Interrupt Enable

When this bit is set, an interrupt is generated when PSC reaches the end of the whole

cycle.

Bit

PSEIE0

PEVE0B

PEVE0A

PEOPE0

PIM0

Read/Write

R/W

Initial Value

Bit

PSEIE1

PEVE1B

PEVE1A

PEOPE1

PIM1

Read/Write

R/W

Initial Value

Bit

PSEIE2

PEVE2B

PEVE2A

PEOPE2

PIM2

Read/Write

R/W

Initial Value

AT90PWM2 Datasheet(PDF) 179 Page - ATMEL Corporation

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