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AT90PWM2 Datasheet(PDF) 181 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 181 Page - ATMEL Corporation |
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181 / 365 page  181 AT90PWM2/3 4317A-3–AVR–02/05 • Bit 3 – PEVnA : PSC n External Event A Interrupt This bit is set by hardware when an external event which can generates a capture or a retrigger from Retrigger/Fault block A occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVEnA bit = 0). • Bit 2:1 – PRNn1:0 : PSC n Ramp Number Memorization of the ramp number when the last PEVnA or PEVnB occured. • Bit 0 – PEOPn: End Of PSC n Interrupt This bit is set by hardware when PSC n achieves its whole cycle. Must be cleared by software by writing a one to its location. Table 69. PSC n Ramp Number Description PnRN1 PnRN0 Description 0 0 The last event which has generated an interrupt occured during ramp 1 0 1 The last event which has generated an interrupt occured during ramp 2 1 0 The last event which has generated an interrupt occured during ramp 3 1 1 The last event which has generated an interrupt occured during ramp 4 |
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